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mirror of https://github.com/wfjm/w11.git synced 2026-04-16 01:30:43 +00:00
Files
wfjm.w11/rtl
wfjm 14362b2a56 Add basic DDR memory support
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
2018-12-31 10:00:14 +01:00
..
2018-12-31 10:00:14 +01:00
2016-12-26 21:27:33 +01:00
2018-12-26 09:40:03 +01:00
2018-12-29 14:14:08 +01:00
2018-12-31 10:00:14 +01:00
2016-12-17 20:18:29 +01:00
2016-12-23 15:51:48 +01:00

This directory tree contains all HDL sources and is organized in

Directory Content
bplib support modules for boards or parts
ibus w11 ibus devices
make_ise make includes for ISE build flows
make_viv make includes for Vivado build flows
sys_gen HDL sources for top level designs
vlib wide range of support modules
w11a HDL sources for w11a core