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23 lines
1.2 KiB
Markdown
23 lines
1.2 KiB
Markdown
## Known differences between w11a and KB11-C (11/70)
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### `MMR0` instruction complete implementation differences
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The 11/70 and 11/45 are the only PDP-11 processors that also support the
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recovery of an MMU abort of a stack push during trap or interrupt processing.
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To distinguish between an instruction and a trap processing abort, the
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`MMR0` has a bit called `instruction completed`. It is set to 0
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when an instruction is aborted and to 1 when a vector service flow is
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aborted. The `MMR2` contains the vector address in the latter case.
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w11 supports this feature, but has two implementation differences:
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- the `instruction completed` flag is set and `MMR2` is loaded with the vector
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address for _all_ vector flows. The 11/70 does this only for traps,
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aborts and interrupts, but not for trap instructions (`BPT`, `IOT`,
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`TRAP`, `EMT`).
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- the w11 decrements the `SP` before each vector push, while the 11/70
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decrements the `SP` twice before the 1st vector push. Therefore, after an
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MMU abort of the 1st vector push, `MMR1` has `000336` on the w11 and `173366`
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on the 11/70.
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xxdp program `ekbee1` test 067 checks this `MMR1` response and has been
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modified (see [patch](../tools/xxdp/ekbee1_patch_w11a.tcl)).
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