mirror of
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1401e20a2e
- rtl/vlib/rlink/tbcore/rlink_cext_dpi.c: add function prototypes - rtl/sys_gen/tst_rlink/cmoda7/tb: add missing ssim vbom - tools/bin - ti_w11: update --help text, add -ar,-n4d,-bn4d - tmuconv: add DEUNA defs
79 lines
3.8 KiB
Markdown
79 lines
3.8 KiB
Markdown
# w11: PDP 11/70 CPU and SoC
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[](https://github.com/wfjm/w11/actions/workflows/ci.yml)
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[](https://scan.coverity.com/projects/wfjm-w11)
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[](https://github.com/wfjm/w11/releases)
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### Overview
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The project contains the VHDL code for a **complete DEC PDP-11 system**:
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a
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[PDP-11/70](http://www.bitsavers.org/pdf/dec/pdp11/1170/EK-KB11C-TM-001_1170procMan.pdf)
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CPU with memory management unit, but without floating point unit,
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a complete set of mass storage peripherals
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([RK11/RK05](http://www.bitsavers.org/pdf/dec/unibus/RK11-C_manual1971.pdf),
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[RL11/RL02](http://www.bitsavers.org/pdf/dec/disc/rl01_rl02/EK-RL122-TM-001_techAug82.pdf),
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[RH70](http://www.bitsavers.org/pdf/dec/unibus/CSS-MO-F-5.2-27_RH70_Option_Description_Feb77.pdf)/[RP06](http://www.bitsavers.org/pdf/dec/disc/rp04_rp05_rp06/EK-RP056-MM-01_maint_Dec75.pdf),
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[TM11/TU10](http://www.bitsavers.org/pdf/dec/magtape/tm11/TM11_Manual.pdf))
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and a rather complete set of UNIBUS peripherals
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([DL11](http://www.bitsavers.org/pdf/dec/unibus/EK-DL11-TM-003_DL11_Asynchronous_Line_Interface_Manual_Sep75.pdf),
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[LP11](http://www.bitsavers.org/pdf/dec/unibus/LP11_UsersMan.pdf),
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[PC11](http://www.bitsavers.org/pdf/dec/unibus/PC11_Reader-Punch_Manual.pdf),
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[DZ11](http://www.bitsavers.org/pdf/dec/unibus/EK-DZ110-TM-002_DZ11_Asynchronous_Multiplexer_Technical_Manual_Oct78.pdf), and
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[DEUNA](http://www.bitsavers.org/pdf/dec/unibus/EK-DEUNA-TM-PRE_TechMan_Dec82.pdf)),
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and last but not least a cache and memory controllers for SRAM, PSRAM and
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SDRAM (via Xilinx MIG core).
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The design is **FPGA proven**, runs currently on Digilent
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[Arty A7](rtl/sys_gen/w11a/arty),
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[Basys3](rtl/sys_gen/w11a/basys3),
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[Cmod A7](rtl/sys_gen/w11a/cmoda7),
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[Nexys A7](rtl/sys_gen/w11a/nexys4d),
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[Nexys4](rtl/sys_gen/w11a/nexys4),
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[Nexys3](rtl/sys_gen/w11a/nexys3),
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[Nexys2](rtl/sys_gen/w11a/nexys2) and
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[S3board](rtl/sys_gen/w11a/s3board)
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boards and boots 5th Edition UNIX and 2.11BSD UNIX.
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For more information look into:
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- w11 project [home page](https://wfjm.github.io/home/w11/)
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and [blog](https://wfjm.github.io/blogs/w11/)
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- [change log](doc/CHANGELOG.md)
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and [installation notes](doc/INSTALL.md)
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- guides to build bit files and test benches
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with [Xilinx Vivado](doc/README_buildsystem_Vivado.md)
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and [Xilinx ISE](doc/README_buildsystem_ISE.md)
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- guides to [run test benches](doc/w11a_tb_guide.md)
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and to [boot operating systems](doc/w11a_os_guide.md)
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- known [issues](doc/README_known_issues.md)
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- known [differences](doc/w11a_known_differences.md)
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- the impatient readers can try their luck with the
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[quick start guide](doc/INSTALL_quickstart.md)
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A short description of the directory layout
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[is provided separately](https://wfjm.github.io/home/w11/impl/dirlayout.html),
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the top-level directories are
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| Directory | Content |
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| --------- | ------- |
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| [doc](doc) | documentation |
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| [rtl](rtl) | HDL sources (mostly VHDL) |
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| [tools](tools) | many tools |
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### Note on freecores/w11
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The [freecores team](http://freecores.github.io/) created in 2014 a
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copy of almost all OpenCores cores in Github under
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[freecores](https://github.com/freecores). This created
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[freecores/w11](https://github.com/freecores/w11)
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which is
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[*outdated* and *not maintained*](https://github.com/freecores/w11/issues/1).
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***Only [wfjm/w11](https://github.com/wfjm/w11) is maintained***.
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### License
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This project is released under the
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[GPL V3 license](https://www.gnu.org/licenses/gpl-3.0.html),
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all files contain an [SPDX](https://spdx.org/)-style disclaimer:
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SPDX-License-Identifier: GPL-3.0-or-later
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The full text of the GPL license is in this directory as
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[License.txt](License.txt).
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