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wfjm.w11/rtl/vlib
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wfjm 8d323848b3 Some minor updates 
- top-level Makefile: drop w11a/arty_bram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- *.Doxyfile: bump version to 0.77
- comment and docu updates
2019-02-24 12:50:38 +01:00
..
cdclib
Add memory tester for Arty and MIG
2019-01-03 09:15:07 +01:00
comlib
comment&code cosmetics; minor changes
2018-11-11 09:50:46 +01:00
genlib
comment&code cosmetics; minor changes
2018-11-11 09:50:46 +01:00
memlib
Some minor updates
2019-02-24 12:50:38 +01:00
rbus
rbd_tester: use fifo_simple_dram
2019-02-23 09:37:19 +01:00
rlink
rbd_tester: use fifo_simple_dram
2019-02-23 09:37:19 +01:00
serport
consolidate clock generation in 7-Series designs
2018-12-21 09:06:16 +01:00
simlib
add memlib/fifo_simple_dram + test benches
2019-02-22 19:09:42 +01:00
xlib
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
generic_clk_100mhz.xdc
Fix license disclaimer
2016-12-26 21:27:33 +01:00
README.md
docu tune-ups; some more README.md
2016-12-23 15:51:48 +01:00
rutil.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
slvtypes.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00

README.md

This directory sub-tree contains a wide range of support modules and is organized in

Directory Content
cdclib modules for clock domain crossing
comlib modules for communication
genlib grab bag of other modules
memlib wrappers for distributed and block RAM; fifos
rbus modules for rbus fabric; some basic rbus devices
rlink rlink interface
serport serial port interface
simlib helper modules for test benches
xlib warppers for some Xilinx components