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wfjm.w11/doc/simh_diff_traced-rti-rtt.md
wfjm 67437bf140 minor cleanups; update vmfset and imfset 
- Makefile: drop ISE targets except for w11a
- rtl/sys_gen/**/*.*mfset: accomodate recent changes
- rtl/w11a
  - pdp11_dpath.vhd: remove PCOUT port
  - pdp11_sequencer.vhd: remove PC port
2022-12-27 13:32:12 +01:00

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Known differences between SimH, 11/70, and w11a

SimH: traced RTI/RTT that clears tbit does trap

On an 11/70 and on a J11, a traced RTI or RTT loading a new PS with tbit=0 does not cause a tbit trap. More precisely:

  • an RTT will never end with a tbit trap
  • an RTI ends with a tbit trap only when the new PS has tbit=0.

The Processor Handbook documentation is misleading and at one point simply wrong.

On SimH, a traced RTI or RTT does trap. Confirmed deficiency, will be fixed.

The w11 implements traced RTI or RTT correctly, the corresponding test is skipped when executed on SimH (see cpu_details.mac test A4.4 part 8).

Tested with SimH V3.12-3.