3.1 KiB
Summary of known differences and limitations for w11a CPU and systems
This file lists the differences and limitations of the w11 CPU and systems. The issues of the w11 CPU and systems are listed in a separate document README_known_issues.md.
Known differences between w11a and KB11-C (11/70)
- Instruction fetch after
SPL - 'fatal stack errors' lose PSW
- Stack limit checks done independent of register set
- 'instruction completed flag' in
MMR0is not implemented CLRandSXTdo a writejsr sppushes originalspvalue- 18-bit UNIBUS address space not mapped
- MMU traps not suppressed when MMU register accessed
All points relate to very 11/70 specific behavior, no operating system depends on them, therefore they are considered acceptable implementation differences.
For a comprehensive list of differences between all PDP-11 models consult the PDP-11 Family Differences Table in
- PDP-11 Architecture Handbook (1983) Appendix B p303
- PDP-11 MICRO/PDP-11 Handbook 1983-84 Appendix G p387
- and also PDP-11 family differences appendix
Differences in unspecified behavior between w11a and KB11-C (11/70)
No software should depend on the unspecified behavior of the CPU, therefore this is considered as an acceptable implementation difference.
Other differences between w11a and KB11-C (11/70)
Known limitations
- some programs use timing loops based on the execution speed of the
original processors. This can lead to spurious timeouts, especially
in old test programs.
--> a 'CPU throttle mechanism' will be added in a future version to circumvent this for some old test codes. - the emulated I/O can lead to apparently slow device reaction times,
especially when the server runs as a normal user process. This can lead
to a timeout, again mostly in test programs.
--> a 'watch dog' mechanism will be added in a future version which suspends the CPU when the server doesn't respond fast enough.
Known differences between w11a and a SimH 11/70
The SimH emulator models only behavior what is relevant for the normal operation of operating systems and user code. Many details which do not have impact on normal operation are not modeled for performance reasons. Test codes are sometimes sensitive to those details, that's why the most relevant are listed here.