mirror of
https://github.com/wfjm/w11.git
synced 2026-01-31 14:12:46 +00:00
cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
183 lines
6.9 KiB
VHDL
183 lines
6.9 KiB
VHDL
-- $Id: genlib.vhd 466 2012-12-30 13:26:55Z mueller $
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--
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-- Copyright 2007-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: genlib
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-- Description: some general purpose components
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--
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 13.3; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2012-12-29 466 1.0.9 add led_pulse_stretch
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-- 2011-11-09 421 1.0.8 add cdc_pulse
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-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
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-- 2010-04-02 273 1.0.6 add timer
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-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
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-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
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-- 2007-12-25 105 1.0.3 RESET:='0' defaults
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-- 2007-06-17 58 1.0.2 added debounce_gen
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-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package genlib is
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component clkdivce is -- generate usec/msec ce pulses
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generic (
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CDUWIDTH : positive := 6; -- usec clock divider width
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USECDIV : positive := 50; -- divider ratio for usec pulse
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MSECDIV : positive := 1000); -- divider ratio for msec pulse
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port (
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CLK : in slbit; -- input clock
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CE_USEC : out slbit; -- usec pulse
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CE_MSEC : out slbit -- msec pulse
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);
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end component;
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component cnt_array_dram is -- counter array, dram based
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generic (
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AWIDTH : positive := 4; -- address width
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- clear counters
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CE : in slv(2**AWIDTH-1 downto 0); -- count enables
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ADDR : out slv(AWIDTH-1 downto 0); -- counter address
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DATA : out slv(DWIDTH-1 downto 0); -- counter data
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ACT : out slbit -- active (not reseting)
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);
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end component;
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component cnt_array_regs is -- counter array, register based
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generic (
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AWIDTH : positive := 4; -- address width
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- clear counters
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CE : in slv(2**AWIDTH-1 downto 0); -- count enables
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ADDR : in slv(AWIDTH-1 downto 0); -- address
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DATA : out slv(DWIDTH-1 downto 0) -- counter data
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);
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end component;
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component debounce_gen is -- debounce, generic vector
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generic (
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CWIDTH : positive := 2; -- clock interval counter width
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CEDIV : positive := 3; -- clock interval divider
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DWIDTH : positive := 8); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_INT : in slbit; -- clock interval enable (usec or msec)
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DI : in slv(DWIDTH-1 downto 0); -- data in
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DO : out slv(DWIDTH-1 downto 0) -- data out
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);
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end component;
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component gray_cnt_gen is -- gray code counter, generic vector
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generic (
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DWIDTH : positive := 4); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv(DWIDTH-1 downto 0) -- data out
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);
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end component;
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component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv4 -- data out
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);
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end component;
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component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv5 -- data out
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);
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end component;
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component gray_cnt_n is -- n bit gray code counter
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generic (
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DWIDTH : positive := 8); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv(DWIDTH-1 downto 0) -- data out
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);
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end component;
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component gray2bin_gen is -- gray->bin converter, generic vector
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generic (
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DWIDTH : positive := 4); -- data width
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port (
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DI : in slv(DWIDTH-1 downto 0); -- gray code input
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DO : out slv(DWIDTH-1 downto 0) -- binary code output
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);
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end component;
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component timer is -- retriggerable timer
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generic (
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TWIDTH : positive := 4; -- timer counter width
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RETRIG : boolean := true); -- re-triggerable true/false
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port (
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CLK : in slbit; -- clock
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CE : in slbit := '1'; -- clock enable
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DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
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START : in slbit; -- start timer
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STOP : in slbit := '0'; -- stop timer
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DONE : out slbit; -- mark last delay cycle
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BUSY : out slbit -- timer running
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);
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end component;
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component cdc_pulse is -- clock domain cross for pulse
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generic (
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POUT_SINGLE : boolean := false; -- if true: single cycle pout
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BUSY_WACK : boolean := false); -- if true: busy waits for ack
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port (
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CLKM : in slbit; -- clock master
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RESET : in slbit := '0'; -- M|reset
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CLKS : in slbit; -- clock slave
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PIN : in slbit; -- M|pulse in
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BUSY : out slbit; -- M|busy
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POUT : out slbit -- S|pulse out
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);
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end component;
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component led_pulse_stretch is -- pulse stretcher for leds
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port (
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CLK : in slbit; -- clock
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CE_INT : in slbit; -- pulse time unit clock enable
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RESET : in slbit := '0'; -- reset
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DIN : in slbit; -- data in
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POUT : out slbit -- pulse out
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);
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end component;
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end package genlib;
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