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cb152cdd33dbbf4c9fb38675001f8af8a8b27143
wfjm.w11/rtl/bplib/arty
History
wfjm 0c3d853a2b add GitHub action; code/comment cosmetics
2022-04-17 19:37:26 +02:00
..
tb
add GitHub action; code/comment cosmetics
2022-04-17 19:37:26 +02:00
arty_pclk.xdc
SPDX: *.xdc
2019-07-26 18:03:23 +02:00
arty_pins.xdc
SPDX: *.xdc
2019-07-26 18:03:23 +02:00
arty_setup.tcl
SPDX: rest
2019-07-26 18:06:36 +02:00
artylib.vhd
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00
mig_a.prj
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
mig_arty.tcl
SPDX: rest
2019-07-26 18:06:36 +02:00
miglib_arty.vbom
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
miglib_arty.vhd
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00
migui_arty_gsim.vbom
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
migui_arty_gsim.vhd
get Nexys A7 working and integrated
2019-08-10 19:03:47 +02:00
sramif_mig_arty.vbom
Add memory tester for Arty and MIG
2019-01-03 09:15:07 +01:00
sramif_mig_arty.vhd
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00