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Some Work

This commit is contained in:
Marcel
2019-09-16 22:32:53 +02:00
parent c89ca69a0e
commit 2a00d64819
9 changed files with 207 additions and 1 deletions

View File

@@ -5,7 +5,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_vi
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd]