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Cleanup

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Gehstock 2018-06-24 16:16:31 +02:00
parent f5504fc57e
commit 2e595b7c68
16 changed files with 0 additions and 22413 deletions
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128
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Assembler report for mz80k_mist
Sun Jun 24 13:31:13 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.sof
6. Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.rbf
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Jun 24 13:31:13 2018 ;
; Revision Name ; mz80k_mist ;
; Top-level Entity Name ; mz80k_mist ;
; Family ; Cyclone III ;
; Device ; EP3C25E144C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; On ; On ;
; Use configuration device ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Enable OCT_DONE ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+---------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------+
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.sof ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.rbf ;
+---------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.sof ;
+----------------+------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------+
; Device ; EP3C25E144C8 ;
; JTAG usercode ; 0x003EEC1B ;
; Checksum ; 0x003EEC1B ;
+----------------+------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.rbf ;
+---------------------+-------------------------------------------------------------------+
; Option ; Setting ;
+---------------------+-------------------------------------------------------------------+
; Raw Binary File ; ;
; Compression Ratio ; 2 ;
+---------------------+-------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sun Jun 24 13:31:10 2018
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4635 megabytes
Info: Processing ended: Sun Jun 24 13:31:13 2018
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03

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/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP3C25E144) Path("D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/") File("mz80k_mist.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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Sun Jun 24 13:31:33 2018

107
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EDA Netlist Writer report for mz80k_mist
Sun Jun 24 13:31:32 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sun Jun 24 13:31:32 2018 ;
; Revision Name ; mz80k_mist ;
; Top-level Entity Name ; mz80k_mist ;
; Family ; Cyclone III ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Tool Name ; ModelSim-Altera (VHDL) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------+
+---------------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------------------------------+
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_85c_slow.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_0c_slow.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_min_1200mv_0c_fast.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_85c_vhd_slow.sdo ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_0c_vhd_slow.sdo ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_min_1200mv_0c_vhd_fast.sdo ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_vhd.sdo ;
+---------------------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sun Jun 24 13:31:27 2018
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
Info (204019): Generated file mz80k_mist_8_1200mv_85c_slow.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_8_1200mv_0c_slow.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_min_1200mv_0c_fast.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_8_1200mv_85c_vhd_slow.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_8_1200mv_0c_vhd_slow.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_min_1200mv_0c_vhd_fast.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_vhd.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4636 megabytes
Info: Processing ended: Sun Jun 24 13:31:32 2018
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04

7777
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8
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
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Fitter Status : Successful - Sun Jun 24 13:31:05 2018
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : mz80k_mist
Top-level Entity Name : mz80k_mist
Family : Cyclone III
Device : EP3C25E144C8
Timing Models : Final
Total logic elements : 3,012 / 24,624 ( 12 % )
Total combinational functions : 2,886 / 24,624 ( 12 % )
Dedicated logic registers : 891 / 24,624 ( 4 % )
Total registers : 891
Total pins : 31 / 83 ( 37 % )
Total virtual pins : 0
Total memory bits : 311,296 / 608,256 ( 51 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )

136
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Flow report for mz80k_mist
Sun Jun 24 13:31:32 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Sun Jun 24 13:31:32 2018 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; mz80k_mist ;
; Top-level Entity Name ; mz80k_mist ;
; Family ; Cyclone III ;
; Device ; EP3C25E144C8 ;
; Timing Models ; Final ;
; Total logic elements ; 3,012 / 24,624 ( 12 % ) ;
; Total combinational functions ; 2,886 / 24,624 ( 12 % ) ;
; Dedicated logic registers ; 891 / 24,624 ( 4 % ) ;
; Total registers ; 891 ;
; Total pins ; 31 / 83 ( 37 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 311,296 / 608,256 ( 51 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+--------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 06/24/2018 13:29:56 ;
; Main task ; Compilation ;
; Revision Name ; mz80k_mist ;
+-------------------+---------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 84440844040061.152983979606548 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PRE_FLOW_SCRIPT_FILE ; quartus_sh:rtl/build_id.tcl ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; Output ; -- ; -- ; -- ;
; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 4725 MB ; 00:00:17 ;
; Fitter ; 00:00:51 ; 2.0 ; 5526 MB ; 00:01:06 ;
; Assembler ; 00:00:03 ; 1.0 ; 4627 MB ; 00:00:03 ;
; TimeQuest Timing Analyzer ; 00:00:10 ; 1.3 ; 4795 MB ; 00:00:12 ;
; EDA Netlist Writer ; 00:00:05 ; 1.0 ; 4636 MB ; 00:00:04 ;
; Total ; 00:01:26 ; -- ; -- ; 00:01:42 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off mz80k_mist -c mz80k_mist
quartus_fit --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
quartus_asm --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
quartus_sta mz80k_mist -c mz80k_mist
quartus_eda --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist

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<sld_project_info>
<project>
<hash md5_digest_80b="29cd8da6179e01d6df0f"/>
</project>
<file_info>
<file device="EP3C25E144C8" path="mz80k_mist.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

3094
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42
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Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_if2" differs only in case from object "S_IF2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_imm1" differs only in case from object "S_IMM1" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_imm2" differs only in case from object "S_IMM2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mr1" differs only in case from object "S_MR1" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mr2" differs only in case from object "S_MR2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_disp" differs only in case from object "S_DISP" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_in" differs only in case from object "S_IN" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_iack" differs only in case from object "S_IACK" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mw1" differs only in case from object "S_MW1" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mw2" differs only in case from object "S_MW2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_out" differs only in case from object "S_OUT" in the same scope
Warning (10268): Verilog HDL information at scandoubler.v(114): always construct contains both blocking and non-blocking assignments
Info (10281): Verilog HDL Declaration information at scandoubler.v(41): object "hq2x" differs only in case from object "Hq2x" in the same scope
Info (10281): Verilog HDL Declaration information at mist_io.v(47): object "SPI_DO" differs only in case from object "spi_do" in the same scope
Warning (10273): Verilog HDL warning at hq2x.sv(247): extended using "x" or "z"
Warning (10230): Verilog HDL assignment warning at mz80k_top.v(30): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at mz80k_top.v(31): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at fz80.v(1085): truncated value with size 16 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at fz80.v(1128): truncated value with size 8 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at fz80.v(1129): truncated value with size 8 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at fz80.v(1458): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at i8253.v(80): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(81): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(84): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(85): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(88): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(89): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(106): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at i8253.v(122): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at i8253.v(138): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at vga.v(42): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at vga.v(44): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(45): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(49): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(53): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(71): truncated value with size 10 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at vga.v(72): truncated value with size 10 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at vga.v(73): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at vga.v(80): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at vga.v(82): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at vga.v(83): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at vga.v(84): truncated value with size 32 to match size of target (1)

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Analysis & Synthesis Status : Successful - Sun Jun 24 13:30:13 2018
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : mz80k_mist
Top-level Entity Name : mz80k_mist
Family : Cyclone III
Total logic elements : 3,152
Total combinational functions : 2,886
Dedicated logic registers : 891
Total registers : 891
Total pins : 31
Total virtual pins : 0
Total memory bits : 311,296
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1

215
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-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
CHIP "mz80k_mist" ASSIGNED TO AN: EP3C25E144C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCCD_PLL3 : 1 : power : : 1.2V : :
GNDA3 : 2 : gnd : : : :
VCCA3 : 3 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 4 : : : : 1 :
VCCINT : 5 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : : : : 1 :
LED : 7 : output : 3.3-V LVTTL : : 1 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : : : : 1 :
nSTATUS : 9 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 :
~ALTERA_DCLK~ / RESERVED_INPUT : 12 : input : 3.3-V LVTTL : : 1 : N
CONF_DATA0 : 13 : input : 3.3-V LVTTL : : 1 : Y
nCONFIG : 14 : : : : 1 :
TDI : 15 : input : : : 1 :
TCK : 16 : input : : : 1 :
VCCIO1 : 17 : power : : 3.3V : 1 :
TMS : 18 : input : : : 1 :
GND : 19 : gnd : : : :
TDO : 20 : output : : : 1 :
nCE : 21 : : : : 1 :
GND+ : 22 : : : : 1 :
GND+ : 23 : : : : 1 :
GND+ : 24 : : : : 2 :
GND+ : 25 : : : : 2 :
VCCIO2 : 26 : power : : 3.3V : 2 :
GND : 27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 :
VCCINT : 29 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 30 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 31 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 32 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 33 : : : : 2 :
VCCINT : 34 : power : : 1.2V : :
VCCA1 : 35 : power : : 2.5V : :
GNDA1 : 36 : gnd : : : :
VCCD_PLL1 : 37 : power : : 1.2V : :
VCCINT : 38 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 :
VCCIO3 : 40 : power : : 3.3V : 3 :
GND : 41 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 :
VCCINT : 45 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 :
VCCIO3 : 47 : power : : 3.3V : 3 :
GND : 48 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 :
GND+ : 52 : : : : 3 :
GND+ : 53 : : : : 3 :
CLOCK_27 : 54 : input : 3.3-V LVTTL : : 4 : Y
GND+ : 55 : : : : 4 :
VCCIO4 : 56 : power : : 3.3V : 4 :
GND : 57 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 :
VCCINT : 61 : power : : 1.2V : :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND : 63 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 :
AUDIO_L : 65 : output : 3.3-V LVTTL : : 4 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 :
VCCINT : 70 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 :
VCCD_PLL4 : 73 : power : : 1.2V : :
GNDA4 : 74 : gnd : : : :
VCCA4 : 75 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 :
VCCINT : 78 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 79 : : : : 5 :
AUDIO_R : 80 : output : 3.3-V LVTTL : : 5 : Y
VCCIO5 : 81 : power : : 3.3V : 5 :
GND : 82 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 :
VCCINT : 84 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 :
SPI_DI : 88 : input : 3.3-V LVTTL : : 5 : Y
GND+ : 89 : : : : 5 :
SPI_SS4 : 90 : input : 3.3-V LVTTL : : 6 : Y
SPI_SS3 : 91 : input : 3.3-V LVTTL : : 6 : Y
CONF_DONE : 92 : : : : 6 :
VCCIO6 : 93 : power : : 3.3V : 6 :
MSEL0 : 94 : : : : 6 :
GND : 95 : gnd : : : :
MSEL1 : 96 : : : : 6 :
MSEL2 : 97 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 101 : : : : 6 :
VCCINT : 102 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 :
SPI_DO : 105 : output : 3.3-V LVTTL : : 6 : Y
VGA_G[0] : 106 : output : 3.3-V LVTTL : : 6 : Y
VCCA2 : 107 : power : : 2.5V : :
GNDA2 : 108 : gnd : : : :
VCCD_PLL2 : 109 : power : : 1.2V : :
VGA_G[1] : 110 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[2] : 111 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[3] : 112 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[4] : 113 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[5] : 114 : output : 3.3-V LVTTL : : 7 : Y
VGA_B[0] : 115 : output : 3.3-V LVTTL : : 7 : Y
VCCINT : 116 : power : : 1.2V : :
VCCIO7 : 117 : power : : 3.3V : 7 :
GND : 118 : gnd : : : :
VGA_HS : 119 : output : 3.3-V LVTTL : : 7 : Y
VGA_B[1] : 120 : output : 3.3-V LVTTL : : 7 : Y
VGA_B[2] : 121 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : 122 : power : : 3.3V : 7 :
GND : 123 : gnd : : : :
VCCINT : 124 : power : : 1.2V : :
VGA_B[3] : 125 : output : 3.3-V LVTTL : : 7 : Y
SPI_SCK : 126 : input : 3.3-V LVTTL : : 7 : Y
SPI_SS2 : 127 : input : 3.3-V LVTTL : : 7 : Y
GND+ : 128 : : : : 8 :
GND+ : 129 : : : : 8 :
VCCIO8 : 130 : power : : 3.3V : 8 :
GND : 131 : gnd : : : :
VGA_B[4] : 132 : output : 3.3-V LVTTL : : 8 : Y
VGA_B[5] : 133 : output : 3.3-V LVTTL : : 8 : Y
VCCINT : 134 : power : : 1.2V : :
VGA_R[0] : 135 : output : 3.3-V LVTTL : : 8 : Y
VGA_VS : 136 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[1] : 137 : output : 3.3-V LVTTL : : 8 : Y
VCCINT : 138 : power : : 1.2V : :
VCCIO8 : 139 : power : : 3.3V : 8 :
GND : 140 : gnd : : : :
VGA_R[2] : 141 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[3] : 142 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[4] : 143 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[5] : 144 : output : 3.3-V LVTTL : : 8 : Y
GND : EPAD : : : : :

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Sharp - MZ-80K_MiST/Output/mz80k_mist.sof
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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -34.936
TNS : -9377.424
Type : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -32.140
TNS : -3694.987
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|CLK_2M'
Slack : -7.401
TNS : -121.075
Type : Slow 1200mV 85C Model Setup 'SPI_SCK'
Slack : -7.006
TNS : -594.451
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|CLK_31250'
Slack : -6.618
TNS : -110.932
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -4.583
TNS : -71.203
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -2.023
TNS : -36.640
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.877
TNS : -2.243
Type : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.412
TNS : -1.310
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|CLK_31250'
Slack : -0.029
TNS : -0.029
Type : Slow 1200mV 85C Model Hold 'SPI_SCK'
Slack : 0.449
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|CLK_2M'
Slack : 0.453
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : 0.675
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : 0.735
TNS : 0.000
Type : Slow 1200mV 85C Model Recovery 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -2.223
TNS : -153.204
Type : Slow 1200mV 85C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 14.024
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'mz80k_top:mz80k_top|clk_count[2]'
Slack : 0.336
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.796
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'SPI_SCK'
Slack : -3.201
TNS : -217.003
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -1.487
TNS : -486.249
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.487
TNS : -29.740
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_2M'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_31250'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.487
TNS : -23.792
Type : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 9.666
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_27'
Slack : 18.366
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -33.231
TNS : -8921.813
Type : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -30.351
TNS : -3422.841
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_2M'
Slack : -6.888
TNS : -112.587
Type : Slow 1200mV 0C Model Setup 'SPI_SCK'
Slack : -6.568
TNS : -550.906
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_31250'
Slack : -6.055
TNS : -101.552
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -4.189
TNS : -65.009
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.811
TNS : -32.260
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.741
TNS : -2.003
Type : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.535
TNS : -1.806
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_31250'
Slack : 0.024
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'SPI_SCK'
Slack : 0.402
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_2M'
Slack : 0.403
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : 0.615
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : 0.658
TNS : 0.000
Type : Slow 1200mV 0C Model Recovery 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -2.150
TNS : -148.220
Type : Slow 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 14.497
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'mz80k_top:mz80k_top|clk_count[2]'
Slack : 0.319
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.316
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'SPI_SCK'
Slack : -3.201
TNS : -217.003
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -1.487
TNS : -486.596
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.487
TNS : -29.740
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_2M'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_31250'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.487
TNS : -23.792
Type : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 9.638
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_27'
Slack : 18.351
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -14.921
TNS : -4020.444
Type : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -14.623
TNS : -1714.893
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_2M'
Slack : -2.558
TNS : -41.495
Type : Fast 1200mV 0C Model Setup 'SPI_SCK'
Slack : -2.408
TNS : -184.558
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_31250'
Slack : -2.296
TNS : -38.342
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.305
TNS : -20.020
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -0.305
TNS : -4.130
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.646
TNS : -4.158
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_31250'
Slack : -0.187
TNS : -0.187
Type : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.063
TNS : -0.175
Type : Fast 1200mV 0C Model Hold 'SPI_SCK'
Slack : 0.147
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_2M'
Slack : 0.187
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : 0.275
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : 0.280
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.886
TNS : -60.997
Type : Fast 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 17.326
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.025
TNS : -1.350
Type : Fast 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.184
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'SPI_SCK'
Slack : -3.000
TNS : -181.072
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -1.000
TNS : -327.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.000
TNS : -20.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_2M'
Slack : -1.000
TNS : -17.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_31250'
Slack : -1.000
TNS : -17.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.000
TNS : -16.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 9.746
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_27'
Slack : 17.928
TNS : 0.000
------------------------------------------------------------