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add Commen Units

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Marcel
2019-07-22 23:42:05 +02:00
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371
common/Memory/dpSDRAM16Mb.vhd Normal file
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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- Emulacao memoria dual-port para SDRAMs
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dpSDRAM16Mb is
generic (
freq_g : integer := 100
);
port (
clock_i : in std_logic;
reset_i : in std_logic;
refresh_i : in std_logic := '1';
-- Porta 0
port0_cs_i : in std_logic;
port0_oe_i : in std_logic;
port0_we_i : in std_logic;
port0_addr_i : in std_logic_vector(20 downto 0);
port0_data_i : in std_logic_vector( 7 downto 0);
port0_data_o : out std_logic_vector( 7 downto 0);
-- Porta 1
port1_cs_i : in std_logic;
port1_oe_i : in std_logic;
port1_we_i : in std_logic;
port1_addr_i : in std_logic_vector(20 downto 0);
port1_data_i : in std_logic_vector( 7 downto 0);
port1_data_o : out std_logic_vector( 7 downto 0);
-- SD-RAM ports
mem_cke_o : out std_logic;
mem_cs_n_o : out std_logic;
mem_ras_n_o : out std_logic;
mem_cas_n_o : out std_logic;
mem_we_n_o : out std_logic;
mem_udq_o : out std_logic;
mem_ldq_o : out std_logic;
mem_ba_o : out std_logic;
mem_addr_o : out std_logic_vector(10 downto 0);
mem_data_io : inout std_logic_vector(15 downto 0)
);
end entity;
architecture Behavior of dpSDRAM16Mb is
constant SdrCmd_de_c : std_logic_vector(3 downto 0) := "1111"; -- deselect
constant SdrCmd_xx_c : std_logic_vector(3 downto 0) := "0111"; -- no operation
constant SdrCmd_rd_c : std_logic_vector(3 downto 0) := "0101"; -- read
constant SdrCmd_wr_c : std_logic_vector(3 downto 0) := "0100"; -- write
constant SdrCmd_ac_c : std_logic_vector(3 downto 0) := "0011"; -- activate
constant SdrCmd_pr_c : std_logic_vector(3 downto 0) := "0010"; -- precharge all
constant SdrCmd_re_c : std_logic_vector(3 downto 0) := "0001"; -- refresh
constant SdrCmd_ms_c : std_logic_vector(3 downto 0) := "0000"; -- mode regiser set
-- SD-RAM control signals
signal SdrCmd_s : std_logic_vector(3 downto 0);
signal SdrBa_s : std_logic;
signal SdrUdq_s : std_logic;
signal SdrLdq_s : std_logic;
signal SdrAdr_s : std_logic_vector(10 downto 0);
signal SdrDat_s : std_logic_vector(15 downto 0);
signal ram0_req_s : std_logic;
signal ram0_ack_s : std_logic;
signal ram0_addr_s : std_logic_vector(20 downto 0);
signal ram0_din_s : std_logic_vector( 7 downto 0);
signal ram0_dout_s : std_logic_vector( 7 downto 0);
signal ram0_we_s : std_logic;
signal ram1_req_s : std_logic;
signal ram1_ack_s : std_logic;
signal ram1_addr_s : std_logic_vector(20 downto 0);
signal ram1_din_s : std_logic_vector( 7 downto 0);
signal ram1_dout_s : std_logic_vector( 7 downto 0);
signal ram1_we_s : std_logic;
begin
-- Detectar pedido na porta 0
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acesso_v : std_logic;
begin
if reset_i = '1' then
port0_data_o <= (others => '1');
ram0_we_s <= '0';
ram0_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram0_req_s = '1' and ram0_ack_s = '1' then
if ram0_we_s = '0' then
port0_data_o <= ram0_dout_s;
end if;
ram0_req_s <= '0';
end if;
if pcs_v = "01" then
ram0_addr_s <= port0_addr_i;
ram0_req_s <= '1';
if port0_we_i = '1' then
ram0_din_s <= port0_data_i;
ram0_we_s <= '1';
else
ram0_we_s <= '0';
end if;
end if;
acesso_v := port0_cs_i and (port0_oe_i or port0_we_i);
pcs_v := pcs_v(0) & acesso_v;
end if;
end process;
-- Detectar pedido na porta 1
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acesso_v : std_logic;
begin
if reset_i = '1' then
port1_data_o <= (others => '1');
ram1_we_s <= '0';
ram1_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram1_req_s = '1' and ram1_ack_s = '1' then
if ram1_we_s = '0' then
port1_data_o <= ram1_dout_s;
end if;
ram1_req_s <= '0';
end if;
if pcs_v = "01" then
ram1_addr_s <= port1_addr_i;
ram1_req_s <= '1';
if port1_we_i = '1' then
ram1_din_s <= port1_data_i;
ram1_we_s <= '1';
else
ram1_we_s <= '0';
end if;
end if;
acesso_v := port1_cs_i and (port1_oe_i or port1_we_i);
pcs_v := pcs_v(0) & acesso_v;
end if;
end process;
----------------------------
process (clock_i)
type typSdrRoutine_t is ( SdrRoutine_Null, SdrRoutine_Init, SdrRoutine_Idle, SdrRoutine_RefreshAll, SdrRoutine_ReadOne, SdrRoutine_WriteOne );
variable SdrRoutine_v : typSdrRoutine_t := SdrRoutine_Null;
variable SdrRoutineSeq_v : unsigned( 7 downto 0) := X"00";
variable refreshDelayCounter_v : unsigned(23 downto 0) := x"000000";
variable SdrRefreshCounter_v : unsigned(15 downto 0) := X"0000";
variable SdrPort_v : std_logic := '0';
variable SdrAddress_v : std_logic_vector(20 downto 0);
begin
if rising_edge(clock_i) then
ram0_ack_s <= '0';
ram1_ack_s <= '0';
case SdrRoutine_v is
when SdrRoutine_Null =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if refreshDelayCounter_v = 0 then
SdrRoutine_v := SdrRoutine_Init;
end if;
when SdrRoutine_Init =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_pr_c;
SdrAdr_s <= (others => '1');
SdrBa_s <= '0';
SdrUdq_s <= '1';
SdrLdq_s <= '1';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"04" or SdrRoutineSeq_v = X"0C" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"14" then
SdrCmd_s <= SdrCmd_ms_c;
SdrAdr_s <= "0000" & "010" & "0" & "000"; -- CAS Latency=2, WT=0(seq), BL=1
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"17" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_Idle =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if ram0_req_s = '1' and ram0_ack_s = '0' then
SdrPort_v := '0';
SdrAddress_v := ram0_addr_s;
if ram0_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif ram1_req_s = '1' and ram1_ack_s = '0' then
SdrPort_v := '1';
SdrAddress_v := ram1_addr_s;
if ram1_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif SdrRefreshCounter_v < 2048 and refresh_i = '1' then
SdrRoutine_v := SdrRoutine_RefreshAll;
SdrRefreshCounter_v := SdrRefreshCounter_v + 1;
end if;
when SdrRoutine_RefreshAll =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_ReadOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(20);
SdrAdr_s <= SdrAddress_v(19 downto 9); -- Row (11 bits)
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_rd_c;
SdrAdr_s(10 downto 8) <= "100"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(7 downto 0) <= SdrAddress_v(8 downto 1); -- Col (8 bits)
SdrUdq_s <= '0';
SdrLdq_s <= '0';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
if SdrPort_v = '0' then
if SdrAddress_v(0) = '0' then
ram0_dout_s <= mem_data_io(7 downto 0);
else
ram0_dout_s <= mem_data_io(15 downto 8);
end if;
ram0_ack_s <= '1';
else
if SdrAddress_v(0) = '0' then
ram1_dout_s <= mem_data_io(7 downto 0);
else
ram1_dout_s <= mem_data_io(15 downto 8);
end if;
ram1_ack_s <= '1';
end if;
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_WriteOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(20);
SdrAdr_s <= SdrAddress_v(19 downto 9);
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_wr_c;
SdrAdr_s(10 downto 8) <= "100"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(7 downto 0) <= SdrAddress_v(8 downto 1);
SdrUdq_s <= not SdrAddress_v(0);
SdrLdq_s <= SdrAddress_v(0);
if SdrPort_v = '0' then
SdrDat_s <= ram0_din_s & ram0_din_s;
else
SdrDat_s <= ram1_din_s & ram1_din_s;
end if;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"03" then
if SdrPort_v = '0' then
ram0_ack_s <= '1';
else
ram1_ack_s <= '1';
end if;
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
end case;
refreshDelayCounter_v := refreshDelayCounter_v + 1;
if refreshDelayCounter_v >= ( freq_g * 1000 * 32 ) then
refreshDelayCounter_v := x"000000";
SdrRefreshCounter_v := x"0000";
end if;
end if;
end process;
mem_cke_o <= '1';
mem_cs_n_o <= SdrCmd_s(3);
mem_ras_n_o <= SdrCmd_s(2);
mem_cas_n_o <= SdrCmd_s(1);
mem_we_n_o <= SdrCmd_s(0);
mem_udq_o <= SdrUdq_s;
mem_ldq_o <= SdrLdq_s;
mem_ba_o <= SdrBa_s;
mem_addr_o <= SdrAdr_s;
mem_data_io <= SdrDat_s;
end architecture;

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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- Emulacao memoria dual-port para SDRAMs
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dpSDRAM256Mb is
generic (
freq_g : integer := 100
);
port (
clock_i : in std_logic;
reset_i : in std_logic;
refresh_i : in std_logic := '1';
-- Port 0
port0_cs_i : in std_logic;
port0_oe_i : in std_logic;
port0_we_i : in std_logic;
port0_addr_i : in std_logic_vector(24 downto 0);
port0_data_i : in std_logic_vector( 7 downto 0);
port0_data_o : out std_logic_vector( 7 downto 0);
-- Port 1
port1_cs_i : in std_logic;
port1_oe_i : in std_logic;
port1_we_i : in std_logic;
port1_addr_i : in std_logic_vector(24 downto 0);
port1_data_i : in std_logic_vector( 7 downto 0);
port1_data_o : out std_logic_vector( 7 downto 0);
-- SDRAM in board
mem_cke_o : out std_logic;
mem_cs_n_o : out std_logic;
mem_ras_n_o : out std_logic;
mem_cas_n_o : out std_logic;
mem_we_n_o : out std_logic;
mem_udq_o : out std_logic;
mem_ldq_o : out std_logic;
mem_ba_o : out std_logic_vector( 1 downto 0);
mem_addr_o : out std_logic_vector(12 downto 0);
mem_data_io : inout std_logic_vector(15 downto 0)
);
end entity;
architecture Behavior of dpSDRAM256Mb is
constant SdrCmd_de_c : std_logic_vector(3 downto 0) := "1111"; -- deselect
constant SdrCmd_xx_c : std_logic_vector(3 downto 0) := "0111"; -- no operation
constant SdrCmd_rd_c : std_logic_vector(3 downto 0) := "0101"; -- read
constant SdrCmd_wr_c : std_logic_vector(3 downto 0) := "0100"; -- write
constant SdrCmd_ac_c : std_logic_vector(3 downto 0) := "0011"; -- activate
constant SdrCmd_pr_c : std_logic_vector(3 downto 0) := "0010"; -- precharge all
constant SdrCmd_re_c : std_logic_vector(3 downto 0) := "0001"; -- refresh
constant SdrCmd_ms_c : std_logic_vector(3 downto 0) := "0000"; -- mode regiser set
-- SD-RAM control signals
signal SdrCmd_s : std_logic_vector(3 downto 0);
signal SdrBa_s : std_logic_vector(1 downto 0);
signal SdrUdq_s : std_logic;
signal SdrLdq_s : std_logic;
signal SdrAdr_s : std_logic_vector(12 downto 0);
signal SdrDat_s : std_logic_vector(15 downto 0);
signal ram0_req_s : std_logic;
signal ram0_ack_s : std_logic;
signal ram0_addr_s : std_logic_vector(24 downto 0);
signal ram0_din_s : std_logic_vector( 7 downto 0);
signal ram0_dout_s : std_logic_vector( 7 downto 0);
signal ram0_we_s : std_logic;
signal ram1_req_s : std_logic;
signal ram1_ack_s : std_logic;
signal ram1_addr_s : std_logic_vector(24 downto 0);
signal ram1_din_s : std_logic_vector( 7 downto 0);
signal ram1_dout_s : std_logic_vector( 7 downto 0);
signal ram1_we_s : std_logic;
begin
-- Detectar pedido na porta 0
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acesso_v : std_logic;
begin
if reset_i = '1' then
port0_data_o <= (others => '1');
ram0_we_s <= '0';
ram0_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram0_req_s = '1' and ram0_ack_s = '1' then
if ram0_we_s = '0' then
port0_data_o <= ram0_dout_s;
end if;
ram0_req_s <= '0';
end if;
if pcs_v = "01" then
ram0_addr_s <= port0_addr_i;
ram0_req_s <= '1';
if port0_we_i = '1' then
ram0_din_s <= port0_data_i;
ram0_we_s <= '1';
else
ram0_we_s <= '0';
end if;
end if;
acesso_v := port0_cs_i and (port0_oe_i or port0_we_i);
pcs_v := pcs_v(0) & acesso_v;
end if;
end process;
-- Detectar pedido na porta 1
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acesso_v : std_logic;
begin
if reset_i = '1' then
port1_data_o <= (others => '1');
ram1_we_s <= '0';
ram1_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram1_req_s = '1' and ram1_ack_s = '1' then
if ram1_we_s = '0' then
port1_data_o <= ram1_dout_s;
end if;
ram1_req_s <= '0';
end if;
if pcs_v = "01" then
ram1_addr_s <= port1_addr_i;
ram1_req_s <= '1';
if port1_we_i = '1' then
ram1_din_s <= port1_data_i;
ram1_we_s <= '1';
else
ram1_we_s <= '0';
end if;
end if;
acesso_v := port1_cs_i and (port1_oe_i or port1_we_i);
pcs_v := pcs_v(0) & acesso_v;
end if;
end process;
----------------------------
process (clock_i)
type typSdrRoutine_t is ( SdrRoutine_Null, SdrRoutine_Init, SdrRoutine_Idle, SdrRoutine_RefreshAll, SdrRoutine_ReadOne, SdrRoutine_WriteOne );
variable SdrRoutine_v : typSdrRoutine_t := SdrRoutine_Null;
variable SdrRoutineSeq_v : unsigned(7 downto 0) := X"00";
variable refreshDelayCounter_v : unsigned(23 downto 0) := x"000000";
variable SdrRefreshCounter_v : unsigned(15 downto 0) := X"0000";
variable SdrPort_v : std_logic := '0';
variable SdrAddress_v : std_logic_vector(24 downto 0);
begin
if rising_edge(clock_i) then
ram0_ack_s <= '0';
ram1_ack_s <= '0';
case SdrRoutine_v is
when SdrRoutine_Null =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if refreshDelayCounter_v = 0 then
SdrRoutine_v := SdrRoutine_Init;
end if;
when SdrRoutine_Init =>
if SdrRoutineSeq_v = X"0" then
SdrCmd_s <= SdrCmd_pr_c;
SdrAdr_s <= (others => '1');
SdrBa_s <= "00";
SdrUdq_s <= '1';
SdrLdq_s <= '1';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"04" or SdrRoutineSeq_v = X"0C" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"14" then
SdrCmd_s <= SdrCmd_ms_c;
SdrAdr_s <= "000" & "1" & "00" & "010" & "0" & "000"; -- Single, Standard, CAS Latency=2, WT=0(seq), BL=1
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"17" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_Idle =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if ram0_req_s = '1' and ram0_ack_s = '0' then
SdrPort_v := '0';
SdrAddress_v := ram0_addr_s;
if ram0_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif ram1_req_s = '1' and ram1_ack_s = '0' then
SdrPort_v := '1';
SdrAddress_v := ram1_addr_s;
if ram1_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif SdrRefreshCounter_v < 8192 and refresh_i = '1' then
SdrRoutine_v := SdrRoutine_RefreshAll;
SdrRefreshCounter_v := SdrRefreshCounter_v + 1;
end if;
when SdrRoutine_RefreshAll =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_ReadOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(24 downto 23);
SdrAdr_s <= SdrAddress_v(22 downto 10); -- Row (13 bits)
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_rd_c;
SdrAdr_s(12 downto 9) <= "0010"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(8 downto 0) <= SdrAddress_v(9 downto 1);
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
SdrUdq_s <= '0';
SdrLdq_s <= '0';
elsif SdrRoutineSeq_v = X"05" then
if SdrPort_v = '0' then
if SdrAddress_v(0) = '0' then
ram0_dout_s <= mem_data_io(7 downto 0);
else
ram0_dout_s <= mem_data_io(15 downto 8);
end if;
ram0_ack_s <= '1';
else
if SdrAddress_v(0) = '0' then
ram1_dout_s <= mem_data_io(7 downto 0);
else
ram1_dout_s <= mem_data_io(15 downto 8);
end if;
ram1_ack_s <= '1';
end if;
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_WriteOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(24 downto 23);
SdrAdr_s <= SdrAddress_v(22 downto 10);
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_wr_c;
SdrAdr_s(12 downto 9) <= "0010"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(8 downto 0) <= SdrAddress_v(9 downto 1);
SdrUdq_s <= not SdrAddress_v(0);
SdrLdq_s <= SdrAddress_v(0);
if SdrPort_v = '0' then
SdrDat_s <= ram0_din_s & ram0_din_s;
else
SdrDat_s <= ram1_din_s & ram1_din_s;
end if;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"03" then
if SdrPort_v = '0' then
ram0_ack_s <= '1';
else
ram1_ack_s <= '1';
end if;
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
end case;
refreshDelayCounter_v := refreshDelayCounter_v + 1;
if refreshDelayCounter_v >= ( freq_g * 1000 * 64 ) then
refreshDelayCounter_v := x"000000";
SdrRefreshCounter_v := x"0000";
end if;
end if;
end process;
mem_cke_o <= '1';
mem_cs_n_o <= SdrCmd_s(3);
mem_ras_n_o <= SdrCmd_s(2);
mem_cas_n_o <= SdrCmd_s(1);
mem_we_n_o <= SdrCmd_s(0);
mem_udq_o <= SdrUdq_s;
mem_ldq_o <= SdrLdq_s;
mem_ba_o <= SdrBa_s;
mem_addr_o <= SdrAdr_s;
mem_data_io <= SdrDat_s;
end architecture;

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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- SDRAM dual-port emulation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dpSDRAM64Mb is
generic (
freq_g : integer := 100
);
port (
clock_i : in std_logic;
reset_i : in std_logic;
refresh_i : in std_logic := '1';
-- Port 0
port0_cs_i : in std_logic;
port0_oe_i : in std_logic;
port0_we_i : in std_logic;
port0_addr_i : in std_logic_vector(22 downto 0);
port0_data_i : in std_logic_vector( 7 downto 0);
port0_data_o : out std_logic_vector( 7 downto 0);
-- Port 1
port1_cs_i : in std_logic;
port1_oe_i : in std_logic;
port1_we_i : in std_logic;
port1_addr_i : in std_logic_vector(22 downto 0);
port1_data_i : in std_logic_vector( 7 downto 0);
port1_data_o : out std_logic_vector( 7 downto 0);
-- SDRAM in board
mem_cke_o : out std_logic;
mem_cs_n_o : out std_logic;
mem_ras_n_o : out std_logic;
mem_cas_n_o : out std_logic;
mem_we_n_o : out std_logic;
mem_udq_o : out std_logic;
mem_ldq_o : out std_logic;
mem_ba_o : out std_logic_vector( 1 downto 0);
mem_addr_o : out std_logic_vector(11 downto 0);
mem_data_io : inout std_logic_vector(15 downto 0)
);
end entity;
architecture Behavior of dpSDRAM64Mb is
constant SdrCmd_de_c : std_logic_vector(3 downto 0) := "1111"; -- deselect
constant SdrCmd_xx_c : std_logic_vector(3 downto 0) := "0111"; -- no operation
constant SdrCmd_rd_c : std_logic_vector(3 downto 0) := "0101"; -- read
constant SdrCmd_wr_c : std_logic_vector(3 downto 0) := "0100"; -- write
constant SdrCmd_ac_c : std_logic_vector(3 downto 0) := "0011"; -- activate
constant SdrCmd_pr_c : std_logic_vector(3 downto 0) := "0010"; -- precharge all
constant SdrCmd_re_c : std_logic_vector(3 downto 0) := "0001"; -- refresh
constant SdrCmd_ms_c : std_logic_vector(3 downto 0) := "0000"; -- mode regiser set
-- SD-RAM control signals
signal SdrCmd_s : std_logic_vector(3 downto 0);
signal SdrBa_s : std_logic_vector(1 downto 0);
signal SdrUdq_s : std_logic;
signal SdrLdq_s : std_logic;
signal SdrAdr_s : std_logic_vector(11 downto 0);
signal SdrDat_s : std_logic_vector(15 downto 0);
signal ram0_req_s : std_logic;
signal ram0_ack_s : std_logic;
signal ram0_addr_s : std_logic_vector(22 downto 0);
signal ram0_din_s : std_logic_vector( 7 downto 0);
signal ram0_dout_s : std_logic_vector( 7 downto 0);
signal ram0_we_s : std_logic;
signal ram1_req_s : std_logic;
signal ram1_ack_s : std_logic;
signal ram1_addr_s : std_logic_vector(22 downto 0);
signal ram1_din_s : std_logic_vector( 7 downto 0);
signal ram1_dout_s : std_logic_vector( 7 downto 0);
signal ram1_we_s : std_logic;
begin
-- Detectar pedido na porta 0
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acesso_v : std_logic;
begin
if reset_i = '1' then
port0_data_o <= (others => '1');
ram0_we_s <= '0';
ram0_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram0_req_s = '1' and ram0_ack_s = '1' then
if ram0_we_s = '0' then
port0_data_o <= ram0_dout_s;
end if;
ram0_req_s <= '0';
end if;
if pcs_v = "01" then
ram0_addr_s <= port0_addr_i;
ram0_req_s <= '1';
if port0_we_i = '1' then
ram0_din_s <= port0_data_i;
ram0_we_s <= '1';
else
ram0_we_s <= '0';
end if;
end if;
acesso_v := port0_cs_i and (port0_oe_i or port0_we_i);
pcs_v := pcs_v(0) & acesso_v;
end if;
end process;
-- Detectar pedido na porta 1
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acesso_v : std_logic;
begin
if reset_i = '1' then
port1_data_o <= (others => '1');
ram1_we_s <= '0';
ram1_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram1_req_s = '1' and ram1_ack_s = '1' then
if ram1_we_s = '0' then
port1_data_o <= ram1_dout_s;
end if;
ram1_req_s <= '0';
end if;
if pcs_v = "01" then
ram1_addr_s <= port1_addr_i;
ram1_req_s <= '1';
if port1_we_i = '1' then
ram1_din_s <= port1_data_i;
ram1_we_s <= '1';
else
ram1_we_s <= '0';
end if;
end if;
acesso_v := port1_cs_i and (port1_oe_i or port1_we_i);
pcs_v := pcs_v(0) & acesso_v;
end if;
end process;
----------------------------
process (clock_i)
type typSdrRoutine_t is ( SdrRoutine_Null, SdrRoutine_Init, SdrRoutine_Idle, SdrRoutine_RefreshAll, SdrRoutine_ReadOne, SdrRoutine_WriteOne );
variable SdrRoutine_v : typSdrRoutine_t := SdrRoutine_Null;
variable SdrRoutineSeq_v : unsigned( 7 downto 0) := X"00";
variable refreshDelayCounter_v : unsigned(23 downto 0) := x"000000";
variable SdrRefreshCounter_v : unsigned(15 downto 0) := X"0000";
variable SdrPort_v : std_logic := '0';
variable SdrAddress_v : std_logic_vector(22 downto 0);
begin
if rising_edge(clock_i) then
ram0_ack_s <= '0';
ram1_ack_s <= '0';
case SdrRoutine_v is
when SdrRoutine_Null =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if refreshDelayCounter_v = 0 then
SdrRoutine_v := SdrRoutine_Init;
end if;
when SdrRoutine_Init =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_pr_c;
SdrAdr_s <= (others => '1');
SdrBa_s <= "00";
SdrUdq_s <= '1';
SdrLdq_s <= '1';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"04" or SdrRoutineSeq_v = X"0C" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"14" then
SdrCmd_s <= SdrCmd_ms_c;
SdrAdr_s <= "00" & "1" & "00" & "010" & "0" & "000"; -- Single, Standard, CAS Latency=2, WT=0(seq), BL=1
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"17" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_Idle =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if ram0_req_s = '1' and ram0_ack_s = '0' then
SdrPort_v := '0';
SdrAddress_v := ram0_addr_s;
if ram0_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif ram1_req_s = '1' and ram1_ack_s = '0' then
SdrPort_v := '1';
SdrAddress_v := ram1_addr_s;
if ram1_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif SdrRefreshCounter_v < 4096 and refresh_i = '1' then
SdrRoutine_v := SdrRoutine_RefreshAll;
SdrRefreshCounter_v := SdrRefreshCounter_v + 1;
end if;
when SdrRoutine_RefreshAll =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_ReadOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(22 downto 21);
SdrAdr_s <= SdrAddress_v(20 downto 9); -- Row (12 bits)
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_rd_c;
SdrAdr_s(11 downto 8) <= "0100"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(7 downto 0) <= SdrAddress_v(8 downto 1); -- Col (8 bits)
SdrUdq_s <= '0';
SdrLdq_s <= '0';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
if SdrPort_v = '0' then
if SdrAddress_v(0) = '0' then
ram0_dout_s <= mem_data_io(7 downto 0);
else
ram0_dout_s <= mem_data_io(15 downto 8);
end if;
ram0_ack_s <= '1';
else
if SdrAddress_v(0) = '0' then
ram1_dout_s <= mem_data_io(7 downto 0);
else
ram1_dout_s <= mem_data_io(15 downto 8);
end if;
ram1_ack_s <= '1';
end if;
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_WriteOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(22 downto 21);
SdrAdr_s <= SdrAddress_v(20 downto 9);
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_wr_c;
SdrAdr_s(11 downto 8) <= "0100"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(7 downto 0) <= SdrAddress_v(8 downto 1);
SdrUdq_s <= not SdrAddress_v(0);
SdrLdq_s <= SdrAddress_v(0);
if SdrPort_v = '0' then
SdrDat_s <= ram0_din_s & ram0_din_s;
else
SdrDat_s <= ram1_din_s & ram1_din_s;
end if;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"03" then
if SdrPort_v = '0' then
ram0_ack_s <= '1';
else
ram1_ack_s <= '1';
end if;
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
end case;
refreshDelayCounter_v := refreshDelayCounter_v + 1;
if refreshDelayCounter_v >= ( freq_g * 1000 * 64 ) then
refreshDelayCounter_v := x"000000";
SdrRefreshCounter_v := x"0000";
end if;
end if;
end process;
mem_cke_o <= '1';
mem_cs_n_o <= SdrCmd_s(3);
mem_ras_n_o <= SdrCmd_s(2);
mem_cas_n_o <= SdrCmd_s(1);
mem_we_n_o <= SdrCmd_s(0);
mem_udq_o <= SdrUdq_s;
mem_ldq_o <= SdrLdq_s;
mem_ba_o <= SdrBa_s;
mem_addr_o <= SdrAdr_s;
mem_data_io <= SdrDat_s;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
entity dpSRAM_1288 is
port (
clk_i : in std_logic;
-- Porta 0
porta0_addr_i : in std_logic_vector(16 downto 0);
porta0_ce_i : in std_logic;
porta0_oe_i : in std_logic;
porta0_we_i : in std_logic;
porta0_data_i : in std_logic_vector(7 downto 0);
porta0_data_o : out std_logic_vector(7 downto 0);
-- Porta 1
porta1_addr_i : in std_logic_vector(16 downto 0);
porta1_ce_i : in std_logic;
porta1_oe_i : in std_logic;
porta1_we_i : in std_logic;
porta1_data_i : in std_logic_vector(7 downto 0);
porta1_data_o : out std_logic_vector(7 downto 0);
-- Output to SRAM in board
sram_addr_o : out std_logic_vector(16 downto 0);
sram_data_io : inout std_logic_vector(7 downto 0);
sram_ce_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
sram_we_n_o : out std_logic := '1'
);
end entity;
architecture Behavior of dpSRAM_1288 is
signal sram_we_n_s : std_logic;
signal sram_oe_n_s : std_logic;
begin
sram_ce_n_o <= '0'; -- sempre ativa
sram_we_n_o <= sram_we_n_s;
sram_oe_n_o <= sram_oe_n_s;
process (clk_i)
variable state_v : std_logic := '0';
variable p0_ce_v : std_logic_vector(1 downto 0);
variable p1_ce_v : std_logic_vector(1 downto 0);
variable acesso0_v : std_logic;
variable acesso1_v : std_logic;
variable p0_req_v : std_logic := '0';
variable p1_req_v : std_logic := '0';
variable p0_we_v : std_logic := '0';
variable p1_we_v : std_logic := '0';
variable p0_addr_v : std_logic_vector(16 downto 0);
variable p1_addr_v : std_logic_vector(16 downto 0);
variable p0_data_v : std_logic_vector(7 downto 0);
variable p1_data_v : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_i) then
acesso0_v := porta0_ce_i and (porta0_oe_i or porta0_we_i);
acesso1_v := porta1_ce_i and (porta1_oe_i or porta1_we_i);
p0_ce_v := p0_ce_v(0) & acesso0_v;
p1_ce_v := p1_ce_v(0) & acesso1_v;
if p0_ce_v = "01" then -- detecta rising edge do pedido da porta0
p0_req_v := '1'; -- marca que porta0 pediu acesso
p0_we_v := '0'; -- por enquanto eh leitura
p0_addr_v := porta0_addr_i; -- pegamos endereco
if porta0_we_i = '1' then -- se foi gravacao que a porta0 pediu
p0_we_v := '1'; -- marcamos que eh gravacao
p0_data_v := porta0_data_i; -- pegamos dado
end if;
end if;
if p1_ce_v = "01" then -- detecta rising edge do pedido da porta1
p1_req_v := '1'; -- marca que porta1 pediu acesso
p1_we_v := '0'; -- por enquanto eh leitura
p1_addr_v := porta1_addr_i; -- pegamos endereco
if porta1_we_i = '1' then -- se foi gravacao que a porta1 pediu
p1_we_v := '1'; -- marcamos que eh gravacao
p1_data_v := porta1_data_i; -- pegamos dado
end if;
end if;
if state_v = '0' then -- Estado 0
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_addr_o <= p0_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_n_s <= '1';
-- sram_ce_n <= '0';
sram_oe_n_s <= '0';
if p0_we_v = '1' then -- se for gravacao
sram_data_io <= p0_data_v; -- damos o dado para a SRAM
sram_we_n_s <= '0'; -- e dizemos para ela gravar
sram_oe_n_s <= '1';
end if;
state_v := '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_addr_o <= p1_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_n_s <= '1';
-- sram_ce_n <= '0';
sram_oe_n_s <= '0';
if p1_we_v = '1' then -- se for gravacao
sram_data_io <= p1_data_v; -- damos o dado para a SRAM
sram_we_n_s <= '0'; -- e dizemos para ela gravar
sram_oe_n_s <= '1';
end if;
state_v := '1'; -- proximo rising do clock vamos para segundo estado
end if;
elsif state_v = '1' then -- Estado 1
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_we_n_s <= '1';
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p0_we_v = '0' then -- se for leitura
porta0_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
end if;
p0_req_v := '0'; -- limpamos a flag de requisicao da porta0
state_v := '0'; -- voltar para estado 0
sram_oe_n_s <= '1';
-- sram_ce_n <= '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_we_n_s <= '1';
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p1_we_v = '0' then -- se for leitura
porta1_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
end if;
p1_req_v := '0'; -- limpamos a flag de requisicao da porta1
state_v := '0'; -- voltar para estado 0
sram_oe_n_s <= '1';
-- sram_ce_n <= '1';
end if;
end if;
end if;
end process;
end;

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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dpSRAM_25616 is
port (
clk_i : in std_logic;
-- Port 0
porta0_addr_i : in std_logic_vector(18 downto 0);
porta0_ce_i : in std_logic;
porta0_oe_i : in std_logic;
porta0_we_i : in std_logic;
porta0_d_i : in std_logic_vector(7 downto 0);
porta0_d_o : out std_logic_vector(7 downto 0);
-- Port 1
porta1_addr_i : in std_logic_vector(18 downto 0);
porta1_ce_i : in std_logic;
porta1_oe_i : in std_logic;
porta1_we_i : in std_logic;
porta1_d_i : in std_logic_vector(7 downto 0);
porta1_d_o : out std_logic_vector(7 downto 0);
-- SRAM in board
sram_addr_o : out std_logic_vector(17 downto 0);
sram_data_io : inout std_logic_vector(15 downto 0);
sram_ub_o : out std_logic;
sram_lb_o : out std_logic;
sram_ce_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
sram_we_n_o : out std_logic := '1'
);
end entity;
architecture Behavior of dpSRAM_25616 is
signal sram_a_s : std_logic_vector(18 downto 0);
signal sram_d_s : std_logic_vector(7 downto 0);
signal sram_we_s : std_logic;
signal sram_oe_s : std_logic;
begin
sram_ce_n_o <= '0'; -- sempre ativa
sram_oe_n_o <= sram_oe_s;
sram_we_n_o <= sram_we_s;
sram_ub_o <= not sram_a_s(0); -- UB = 0 ativa bits 15..8
sram_lb_o <= sram_a_s(0); -- LB = 0 ativa bits 7..0
sram_addr_o <= sram_a_s(18 downto 1);
sram_data_io <= "ZZZZZZZZ" & sram_d_s when sram_a_s(0) = '0' else
sram_d_s & "ZZZZZZZZ";
process (clk_i)
variable state_v : std_logic := '0';
variable p0_ce_v : std_logic_vector(1 downto 0);
variable p1_ce_v : std_logic_vector(1 downto 0);
variable acesso0_v : std_logic;
variable acesso1_v : std_logic;
variable p0_req_v : std_logic := '0';
variable p1_req_v : std_logic := '0';
variable p0_we_v : std_logic := '0';
variable p1_we_v : std_logic := '0';
variable p0_addr_v : std_logic_vector(18 downto 0);
variable p1_addr_v : std_logic_vector(18 downto 0);
variable p0_data_v : std_logic_vector(7 downto 0);
variable p1_data_v : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_i) then
acesso0_v := porta0_ce_i and (porta0_oe_i or porta0_we_i);
acesso1_v := porta1_ce_i and (porta1_oe_i or porta1_we_i);
p0_ce_v := p0_ce_v(0) & acesso0_v;
p1_ce_v := p1_ce_v(0) & acesso1_v;
if p0_ce_v = "01" then -- detecta rising edge do pedido da porta0
p0_req_v := '1'; -- marca que porta0 pediu acesso
p0_we_v := '0'; -- por enquanto eh leitura
p0_addr_v := porta0_addr_i; -- pegamos endereco
if porta0_we_i = '1' then -- se foi gravacao que a porta0 pediu
p0_we_v := '1'; -- marcamos que eh gravacao
p0_data_v := porta0_d_i; -- pegamos dado
end if;
end if;
if p1_ce_v = "01" then -- detecta rising edge do pedido da porta1
p1_req_v := '1'; -- marca que porta1 pediu acesso
p1_we_v := '0'; -- por enquanto eh leitura
p1_addr_v := porta1_addr_i; -- pegamos endereco
if porta1_we_i = '1' then -- se foi gravacao que a porta1 pediu
p1_we_v := '1'; -- marcamos que eh gravacao
p1_data_v := porta1_d_i; -- pegamos dado
end if;
end if;
if state_v = '0' then -- Estado 0
sram_d_s <= (others => 'Z'); -- desconectar bus da SRAM
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_a_s <= p0_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_s <= '1';
sram_oe_s <= '0';
if p0_we_v = '1' then -- se for gravacao
sram_d_s <= p0_data_v; -- damos o dado para a SRAM
sram_we_s <= '0'; -- e dizemos para ela gravar
sram_oe_s <= '1';
end if;
state_v := '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_a_s <= p1_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_s <= '1';
sram_oe_s <= '0';
if p1_we_v = '1' then -- se for gravacao
sram_d_s <= p1_data_v; -- damos o dado para a SRAM
sram_we_s <= '0'; -- e dizemos para ela gravar
sram_oe_s <= '1';
end if;
state_v := '1'; -- proximo rising do clock vamos para segundo estado
end if;
elsif state_v = '1' then -- Estado 1
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_we_s <= '1';
sram_d_s <= (others => 'Z'); -- desconectar bus da SRAM
if p0_we_v = '0' then -- se for leitura
if sram_a_s(0) = '0' then -- pegamos o dado que a SRAM devolveu
porta0_d_o <= sram_data_io(7 downto 0);
else
porta0_d_o <= sram_data_io(15 downto 8);
end if;
end if;
p0_req_v := '0'; -- limpamos a flag de requisicao da porta0
state_v := '0'; -- voltar para estado 0
sram_oe_s <= '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_we_s <= '1';
sram_d_s <= (others => 'Z'); -- desconectar bus da SRAM
if p1_we_v = '0' then -- se for leitura
if sram_a_s(0) = '0' then -- pegamos o dado que a SRAM devolveu
porta1_d_o <= sram_data_io(7 downto 0);
else
porta1_d_o <= sram_data_io(15 downto 8);
end if;
end if;
p1_req_v := '0'; -- limpamos a flag de requisicao da porta1
state_v := '0'; -- voltar para estado 0
sram_oe_s <= '1';
end if;
end if;
end if;
end process;
end;

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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dpSRAM_5128 is
port (
clk_i : in std_logic;
-- Port 0
porta0_addr_i : in std_logic_vector(18 downto 0);
porta0_ce_i : in std_logic;
porta0_oe_i : in std_logic;
porta0_we_i : in std_logic;
porta0_data_i : in std_logic_vector(7 downto 0);
porta0_data_o : out std_logic_vector(7 downto 0);
-- Port 1
porta1_addr_i : in std_logic_vector(18 downto 0);
porta1_ce_i : in std_logic;
porta1_oe_i : in std_logic;
porta1_we_i : in std_logic;
porta1_data_i : in std_logic_vector(7 downto 0);
porta1_data_o : out std_logic_vector(7 downto 0);
-- SRAM in board
sram_addr_o : out std_logic_vector(18 downto 0);
sram_data_io : inout std_logic_vector(7 downto 0);
sram_ce_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
sram_we_n_o : out std_logic := '1'
);
end entity;
architecture Behavior of dpSRAM_5128 is
signal sram_we_s : std_logic;
signal sram_oe_s : std_logic;
begin
sram_ce_n_o <= '0'; -- sempre ativa
sram_we_n_o <= sram_we_s;
sram_oe_n_o <= sram_oe_s;
process (clk_i)
variable state_v : std_logic := '0';
variable p0_ce_v : std_logic_vector(1 downto 0);
variable p1_ce_v : std_logic_vector(1 downto 0);
variable acesso0_v : std_logic;
variable acesso1_v : std_logic;
variable p0_req_v : std_logic := '0';
variable p1_req_v : std_logic := '0';
variable p0_we_v : std_logic := '0';
variable p1_we_v : std_logic := '0';
variable p0_addr_v : std_logic_vector(18 downto 0);
variable p1_addr_v : std_logic_vector(18 downto 0);
variable p0_data_v : std_logic_vector(7 downto 0);
variable p1_data_v : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_i) then
acesso0_v := porta0_ce_i and (porta0_oe_i or porta0_we_i);
acesso1_v := porta1_ce_i and (porta1_oe_i or porta1_we_i);
p0_ce_v := p0_ce_v(0) & acesso0_v;
p1_ce_v := p1_ce_v(0) & acesso1_v;
if p0_ce_v = "01" then -- detecta rising edge do pedido da porta0
p0_req_v := '1'; -- marca que porta0 pediu acesso
p0_we_v := '0'; -- por enquanto eh leitura
p0_addr_v := porta0_addr_i; -- pegamos endereco
if porta0_we_i = '1' then -- se foi gravacao que a porta0 pediu
p0_we_v := '1'; -- marcamos que eh gravacao
p0_data_v := porta0_data_i; -- pegamos dado
end if;
end if;
if p1_ce_v = "01" then -- detecta rising edge do pedido da porta1
p1_req_v := '1'; -- marca que porta1 pediu acesso
p1_we_v := '0'; -- por enquanto eh leitura
p1_addr_v := porta1_addr_i; -- pegamos endereco
if porta1_we_i = '1' then -- se foi gravacao que a porta1 pediu
p1_we_v := '1'; -- marcamos que eh gravacao
p1_data_v := porta1_data_i; -- pegamos dado
end if;
end if;
if state_v = '0' then -- Estado 0
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_addr_o <= p0_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_s <= '1';
-- sram_ce_n <= '0';
sram_oe_s <= '0';
if p0_we_v = '1' then -- se for gravacao
sram_data_io <= p0_data_v; -- damos o dado para a SRAM
sram_we_s <= '0'; -- e dizemos para ela gravar
sram_oe_s <= '1';
end if;
state_v := '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_addr_o <= p1_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_s <= '1';
-- sram_ce_n <= '0';
sram_oe_s <= '0';
if p1_we_v = '1' then -- se for gravacao
sram_data_io <= p1_data_v; -- damos o dado para a SRAM
sram_we_s <= '0'; -- e dizemos para ela gravar
sram_oe_s <= '1';
end if;
state_v := '1'; -- proximo rising do clock vamos para segundo estado
end if;
elsif state_v = '1' then -- Estado 1
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_we_s <= '1';
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p0_we_v = '0' then -- se for leitura
porta0_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
end if;
p0_req_v := '0'; -- limpamos a flag de requisicao da porta0
state_v := '0'; -- voltar para estado 0
sram_oe_s <= '1';
-- sram_ce_n <= '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_we_s <= '1';
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p1_we_v = '0' then -- se for leitura
porta1_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
end if;
p1_req_v := '0'; -- limpamos a flag de requisicao da porta1
state_v := '0'; -- voltar para estado 0
sram_oe_s <= '1';
-- sram_ce_n <= '1';
end if;
end if;
end if;
end process;
end;

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-------------------------------------------------------------------------------
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
port (
clk_a_i : in std_logic;
we_i : in std_logic;
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
clk_b_i : in std_logic;
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
);
end entity;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dpram is
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of
std_logic_vector(data_width_g-1 downto 0);
signal ram_q : ram_t;
begin
mem_a: process (clk_a_i)
variable read_addr_v : unsigned(addr_width_g-1 downto 0);
begin
if rising_edge(clk_a_i) then
read_addr_v := unsigned(addr_a_i);
if we_i = '1' then
ram_q(to_integer(read_addr_v)) <= data_a_i;
end if;
data_a_o <= ram_q(to_integer(read_addr_v));
end if;
end process mem_a;
mem_b: process (clk_b_i)
variable read_addr_v : unsigned(addr_width_g-1 downto 0);
begin
if rising_edge(clk_b_i) then
read_addr_v := unsigned(addr_b_i);
data_b_o <= ram_q(to_integer(read_addr_v));
end if;
end process mem_b;
end rtl;

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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- Generic single port RAM.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(addr_width_g-1 downto 0);
data_i : in std_logic_vector(data_width_g-1 downto 0);
data_o : out std_logic_vector(data_width_g-1 downto 0)
);
end spram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of spram is
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
signal ram_q : ram_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
signal read_addr_q : unsigned(addr_width_g-1 downto 0);
begin
process (clk_i)
begin
if rising_edge(clk_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end rtl;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
numwords_a : natural := 0; -- not used any more
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;