mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-10 12:28:26 +00:00
Vectrex: use Greg Miller's CPU by default
This commit is contained in:
Gyorgy Szombathelyi
@@ -1,21 +1,18 @@
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GCE(General Consumer Electronics) - Vectrex For Mist FPGA
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Max 16kb Roms supported
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Up to 32kb Roms supported
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Controls:
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Movement: Joystick, Keyboard(Arrow Keys)
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Movement: Joystick
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Buttons: 1-4 on Joystick Fire Buttons
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(Player 1) 1-4 on Keyboard 1-4 and WASD
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(Player 2) NUM, /, *, - on Numpad and Arrow Keys
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ToDo: Reset (hold Button longer for a Correct Reset)
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CPU: It's possible to choose between two CPUs:
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- MC6809 - Greg Miller's cycle exact 6809
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- CPU09 - John Kent's 6809 compatible CPU
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Speech extension can clash with the controls in some games,
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turn off Speech if it happens.
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@@ -138,8 +138,8 @@ port
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clock_24 : in std_logic;
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clock_12 : in std_logic;
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reset : in std_logic;
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cpu : in std_logic; -- 1 - CPU by John Kent, 0 -- CPU by Greg Miller (Cycle exact)
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video_r : out std_logic_vector(3 downto 0);
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video_g : out std_logic_vector(3 downto 0);
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video_b : out std_logic_vector(3 downto 0);
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@@ -205,7 +205,35 @@ architecture syn of vectrex is
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IOB_out : out std_logic_vector(7 downto 0)
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);
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end component;
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component mc6809 is port
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(
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CPU : in std_logic;
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CLK : in std_logic;
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CLKEN : in std_logic;
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E : out std_logic;
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riseE : out std_logic;
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fallE : out std_logic;
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Q : out std_logic;
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riseQ : out std_logic;
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fallQ : out std_logic;
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Din : in std_logic_vector(7 downto 0);
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Dout : out std_logic_vector(7 downto 0);
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ADDR : out std_logic_vector(15 downto 0);
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RnW : out std_logic;
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nIRQ : in std_logic := '1';
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nFIRQ : in std_logic := '1';
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nNMI : in std_logic := '1';
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nHALT : in std_logic := '1';
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nRESET : in std_logic := '1'
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);
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end component mc6809;
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--------------------------------------------------------------
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-- Configuration
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--------------------------------------------------------------
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@@ -406,20 +434,13 @@ end process;
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reset_n <= not reset;
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clock_24n <= not clock_24;
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process (clock_24, reset)
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begin
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if reset='1' then
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clock_div <= "0000";
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else
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if rising_edge(clock_24) then
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clock_div <= clock_div + '1';
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end if;
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process (clock_24) begin
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if rising_edge(clock_24) then
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clock_div <= clock_div + '1';
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end if;
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end process;
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via_en_4 <= '1' when clock_div(1 downto 0) = "11" else '0';
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cpu_clock <= clock_div(3);
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cpu_clock_en <= '1' when clock_div(3 downto 0) = "1111" else '0';
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process (clock_24, reset)
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begin
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@@ -457,7 +478,7 @@ ram_we <= '1' when cpu_rw = '0' and ram_cs = '1' else '0';
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-- misc
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cpu_irq <= not via_irq_n;
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cpu_firq <= '0';
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cpu_firq <= btn14;
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cart_rd <= cart_cs;
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cpu_di <= cart_do when cart_cs = '1' else
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ram_do when ram_cs = '1' else
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@@ -833,29 +854,26 @@ frame <= frame_line;
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---------------------------
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-- microprocessor 6809
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main_cpu : entity work.cpu09
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port map(
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clk => clock_24,-- E clock input (falling edge)
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ce => cpu_clock_en,
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rst => reset, -- reset input (active high)
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vma => open, -- valid memory address (active high)
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lic_out => open, -- last instruction cycle (active high)
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ifetch => open, -- instruction fetch cycle (active high)
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opfetch => cpu_fetch,-- opcode fetch (active high)
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ba => open, -- bus available (high on sync wait or DMA grant)
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bs => open, -- bus status (high on interrupt or reset vector fetch or DMA grant)
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addr => cpu_addr, -- address bus output
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rw => cpu_rw, -- read not write output
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data_out => cpu_do, -- data bus output
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data_in => cpu_di, -- data bus input
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irq => cpu_irq, -- interrupt request input (active high)
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firq => cpu_firq, -- fast interrupt request input (active high)
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nmi => '0', -- non maskable interrupt request input (active high)
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halt => '0'--, -- halt input (active high) grants DMA
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-- hold_in => '0' -- hold input (active high) extend bus cycle
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main_cpu : mc6809
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port map
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(
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CLK => clock_24,
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CLKEN => via_en_4,
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nRESET => not reset,
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CPU => not cpu,
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E => cpu_clock,
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riseQ => cpu_clock_en,
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Din => cpu_di,
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Dout => cpu_do,
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ADDR => cpu_addr,
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RnW => cpu_rw,
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nIRQ => not cpu_irq,
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nFIRQ => not cpu_firq
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);
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cpu_prog_rom : entity work.vectrex_exec_prom
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port map(
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clk => clock_24,
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@@ -941,7 +959,7 @@ port map(
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RESET_L => reset_n,
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CLK => clock_24,
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I_P2_H => cpu_clock, -- high for phase 2 clock ____----__
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I_P2_H => not cpu_clock,-- high for phase 2 clock ____----__
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ENA_4 => via_en_4 -- 4x system clock (4HZ) _-_-_-_-_-
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);
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@@ -33,6 +33,7 @@ module vectrex_mist
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localparam CONF_STR = {
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"Vectrex;BINVECROM;",
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"O1,CPU,MC6809,CPU09;",
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"O2,Show Frame,Yes,No;",
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"O3,Skip Logo,Yes,No;",
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"O4,Joystick swap,Off,On;",
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@@ -101,20 +102,28 @@ sdram cart
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.ready()
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);
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wire reset = (status[0] | status[6] | buttons[1] | ioctl_downl | second_reset);
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reg reset = 0;
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reg second_reset = 0;
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always @(posedge clk_24) begin
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integer timeout = 0;
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reg [15:0] reset_counter = 0;
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reg reset_start;
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if(ioctl_downl && status[3]) timeout <= 5000000;
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else begin
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if(!timeout) second_reset <= 0;
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else begin
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timeout <= timeout - 1;
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if(timeout < 1000) second_reset <= 1;
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end
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reset <= 0;
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reset_start <= status[0] | status[6] | buttons[1] | ioctl_downl | second_reset;
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if (reset_counter) begin
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reset <= 1'b1;
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reset_counter <= reset_counter - 1'd1;
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end
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if (reset_start) reset_counter <= 16'd1000;
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second_reset <= 0;
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if (timeout) begin
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timeout <= timeout - 1;
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if(timeout == 1) second_reset <= 1'b1;
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end
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if(ioctl_downl && !status[3]) timeout <= 5000000;
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end
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assign pot_x_1 = status[4] ? joy_ana_1[15:8] : joy_ana_0[15:8];
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@@ -126,6 +135,7 @@ vectrex vectrex (
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.clock_24 ( clk_24 ),
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.clock_12 ( clk_12 ),
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.reset ( reset ),
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.cpu ( status[1] ),
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.video_r ( rr ),
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.video_g ( gg ),
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.video_b ( bb ),
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@@ -173,8 +183,6 @@ assign r = status[2] & frame_line ? 4'h4 : blankn ? rr : 4'd0;
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assign g = status[2] & frame_line ? 4'h0 : blankn ? gg : 4'd0;
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assign b = status[2] & frame_line ? 4'h0 : blankn ? bb : 4'd0;
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wire vsync_out;
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wire hsync_out;
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wire csync_out = ~(hs ^ vs);
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assign VGA_HS = ypbpr ? csync_out : hs;
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