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Marcel 1ce3729046 Merge pull request #60 from eubrunosilva/master
small fixes to compile cores
2020-01-25 00:38:27 +01:00
2020-01-19 23:39:59 +00:00
2020-01-04 17:07:30 +01:00
2018-01-22 11:32:25 +01:00
2020-01-04 23:30:17 +01:00
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478 MiB
Languages
VHDL 66.6%
Verilog 19.2%
SystemVerilog 11.7%
Tcl 2.1%
Batchfile 0.2%
Other 0.1%