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Marcel 20423d622f Merge pull request #95 from gyurco/master
Some more common components usage
2020-08-13 20:07:50 +02:00
2020-08-09 22:10:56 +02:00
2020-06-19 16:58:23 +02:00
2018-01-22 11:32:25 +01:00
2020-05-13 15:54:31 +02:00
Description
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475 MiB
Languages
VHDL 66.8%
Verilog 19.1%
SystemVerilog 11.6%
Tcl 2.1%
Batchfile 0.2%
Other 0.1%