mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-09 12:05:55 +00:00
4c425ad52a713025c8de0971aa9895cb40a61fe2
- fix pixel clock (actually one clock/core) - don't invert sync, they're negative already - add sdc file to cores
Description
No description provided
Languages
VHDL
66.6%
Verilog
19.2%
SystemVerilog
11.7%
Tcl
2.1%
Batchfile
0.2%
Other
0.1%