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Marcel 7c52d69d88 Merge pull request #56 from gyurco/master
Calipso: use common components, fix controls
2020-01-18 23:47:37 +01:00
2020-01-04 17:07:30 +01:00
2018-01-22 11:32:25 +01:00
2020-01-04 23:30:17 +01:00
Description
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478 MiB
Languages
VHDL 66.6%
Verilog 19.2%
SystemVerilog 11.7%
Tcl 2.1%
Batchfile 0.2%
Other 0.1%