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mirror of synced 2026-03-28 19:12:08 +00:00
Code Issues Releases Wiki Activity

signorm: skip const when fixing fanout

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This commit is contained in:
Emil J. Tywoniak
2026-03-17 11:28:10 +01:00
parent 869a7303b0
commit debc2c3977
1 changed files with 8 additions and 2 deletions
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10
kernel/rtlil_bufnorm.cc
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@@ -143,7 +143,8 @@ struct RTLIL::SigNormIndex
continue;
int i = 0;
for (auto bit : sig)
fanout[bit].insert(PortBit(cell, port, i++));
if (bit.is_wire())
fanout[bit].insert(PortBit(cell, port, i++));
}
}
}
@@ -963,6 +964,8 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
auto &fanout = module->sig_norm_index->fanout;
int counter = 0;
for (auto bit : conn_it->second) {
if (!bit.is_wire())
continue;
int i = counter++;
auto found = fanout.find(bit);
log_assert(found != fanout.end());
@@ -1090,6 +1093,8 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
auto &fanout = module->sig_norm_index->fanout;
int counter = 0;
for (auto bit : conn_it->second) {
if (!bit.is_wire())
continue;
int i = counter++;
auto found = fanout.find(bit);
log_assert(found != fanout.end());
@@ -1111,7 +1116,8 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
auto &fanout = module->sig_norm_index->fanout;
int i = 0;
for (auto bit : signal)
fanout[bit].insert(PortBit(this, portname, i++));
if (bit.is_wire())
fanout[bit].insert(PortBit(this, portname, i++));
} else if (GetSize(signal)) {
Wire *w = signal.as_wire();
log_assert(w->driverCell_ == nullptr);