Lofty
634044842f
analogdevices: update T40LP timings
2026-02-19 10:59:59 +00:00
Lofty
7448e9d93c
analogdevices: update T16FFC timings
2026-02-19 10:59:59 +00:00
Lofty
25b6c9f03a
synth_analogdevices: update timing model and tests
2026-02-19 10:59:59 +00:00
Lofty
f5438f0d76
analogdevices: double LUT RAM cost
2026-02-19 10:59:59 +00:00
Lofty
7a3df0c915
analogdevices: ignore $assert cells
2026-02-19 10:59:59 +00:00
Krystine Sherwin
8ee0a645aa
analogdevices: Extra tests
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`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2026-02-19 10:59:59 +00:00
Krystine Sherwin
183cb49d3d
analogdevices: Fixing up bram
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Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
2026-02-19 10:59:59 +00:00
Krystine Sherwin
71c76c9f43
analogdevices: Add BRAM options
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Enable `-force-params`, and tidy up lutram mapping too.
2026-02-19 10:59:59 +00:00
Krystine Sherwin
9036d42621
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-19 10:59:59 +00:00
Lofty
c6cce2d6e5
analogdevices: LUT RAM only on positive edge
2026-02-19 10:59:59 +00:00
Lofty
00f4e8ae22
analogdevices: DSP tweaks
2026-02-19 10:59:59 +00:00
Lofty
6405061e8d
analogdevices: DSP inference
2026-02-19 10:59:59 +00:00
Lofty
65e70faecb
analogdevices: remove cells_xtra
2026-02-19 10:59:59 +00:00
Lofty
dc6a84143f
analogdevices: timings for t40lp
2026-02-19 10:59:59 +00:00
Lofty
8d03026e38
analogdevices: use single tech param
2026-02-19 10:59:59 +00:00
Lofty
df518afa23
analogdevices: expreso does not care about clock buffers
2026-02-19 10:59:59 +00:00
Lofty
936fdb38e9
analogdevices: prepare for t40lp timings
2026-02-19 10:59:59 +00:00
Krystine Sherwin
ec75c390c3
analogdevices: Adding RBRAM2 and -tech
2026-02-19 10:59:59 +00:00
Krystine Sherwin
68f0014f53
analogdevices: (some) Native BRAM
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Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
2026-02-19 10:59:59 +00:00
Krystine Sherwin
d87c1f61af
analogdevices: Update lutram.ys test
2026-02-19 10:59:59 +00:00
Krystine Sherwin
a3496e9732
analogdevices: Native LUTRAM primitives
2026-02-19 10:59:59 +00:00
Lofty
34f7fad23e
analogdevices: LUTRAM config
2026-02-19 10:59:59 +00:00
Lofty
8e331b7795
analogdevices: update timing model
2026-02-19 10:59:59 +00:00
Lofty
d7b5177d51
I thought I removed this...
2026-02-19 10:59:59 +00:00
Lofty
cd1d70bcd2
analogdevices: user retargeting
2026-02-19 10:59:59 +00:00
Lofty
417bbab31b
analogdevices: more housekeeping
2026-02-19 10:59:59 +00:00
Lofty
e0701750b9
analogdevices: remove some extra cells!
2026-02-19 10:59:59 +00:00
Lofty
c1389b78c2
test suite
2026-02-19 10:59:59 +00:00
Lofty
8c132b6ee1
synth_analogdevices: remove scopeinfo cells
2026-02-19 10:59:59 +00:00
Lofty
8dc5f2b7e0
Create synth_analogdevices
2026-02-19 10:59:59 +00:00
Emil J
33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check
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blifparse: add bounds check
2026-02-18 12:18:05 +01:00
Miodrag Milanović
ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default
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Run unit tests on make test
2026-02-13 15:02:50 +01:00
github-actions[bot]
e2f0c4d9a0
Bump version
2026-02-13 00:35:27 +00:00
Miodrag Milanovic
bb7aa7d208
Cleanup of yml files
2026-02-12 14:56:45 +01:00
Miodrag Milanović
e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult
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Gowin: Add DSP inference for GW1N and GW2A
2026-02-12 14:30:27 +01:00
Miodrag Milanovic
e5b3e9fc1f
This one should run only vanilla-tests
2026-02-12 14:08:49 +01:00
Miodrag Milanovic
c6e48f4bea
These are tests from other Makefile
2026-02-12 14:06:08 +01:00
Miodrag Milanovic
cc79c6a761
Support building out of tree, but keep always in tests/unit
2026-02-12 12:17:07 +01:00
Maxim Kudinov
b055ea05fd
gowin: dsp: Add mult inference tests
2026-02-12 14:12:32 +03:00
Maxim Kudinov
5b94a97fb3
gowin: synth_gowin: Add -nodsp option
2026-02-12 13:58:47 +03:00
Maxim Kudinov
542b29fa6a
gowin: synth_gowin: Merge flatten label with coarse
2026-02-12 13:58:47 +03:00
Maxim Kudinov
5ea073d45e
gowin: format MULT instances
2026-02-12 13:35:49 +03:00
Miodrag Milanović
9b9e7b5ae3
Merge pull request #3389 from uwsampl/support-parameter-default-values-in-json-frontend-and-verilog-backend
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Support parameter default values in JSON frontend and Verilog backend
2026-02-12 10:17:56 +01:00
Miodrag Milanović
ce5321da8c
Merge pull request #5682 from YosysHQ/update_abc
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Update ABC as per 2026-02-11
2026-02-12 08:05:23 +01:00
github-actions[bot]
1319112913
Bump version
2026-02-12 00:32:36 +00:00
Gus Smith
7a0774c3bb
Don't dump params by default
2026-02-11 08:33:39 -08:00
Emil J
b890b1b43f
Merge pull request #5678 from YosysHQ/emil/remove-dockerfile
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Dockerfile: remove
2026-02-11 17:32:21 +01:00
Miodrag Milanovic
a13b5c4211
Update ABC as per 2026-02-11
2026-02-11 17:30:08 +01:00
Gus Smith
be9c857e72
Fix ABC after merge
2026-02-11 08:12:38 -08:00
Gus Smith
b0021e5b10
Add tests
2026-02-11 08:10:57 -08:00
