Emil J. Tywoniak
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98c3f03497
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docs: clarify vanilla test run-test.sh
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2026-02-11 00:58:29 +01:00 |
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Emil J. Tywoniak
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dfbef2fe24
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.github: run unit tests in build jobs, not test jobs
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2026-02-11 00:55:36 +01:00 |
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Krystine Sherwin
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9f30f0e7d6
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test-build: Don't rebuild OBJS
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2026-02-10 15:34:47 +13:00 |
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Krystine Sherwin
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030e495c8b
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test-build: Build and cache libyosys.so
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2026-02-10 15:05:17 +13:00 |
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github-actions[bot]
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a6e33d9916
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Bump version
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2026-02-10 00:38:43 +00:00 |
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Emil J
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d2f7d3cf63
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Merge pull request #5665 from rocallahan/abc-tmp-path
Sanitize ABC global and per-run temporary directory names in logs
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2026-02-09 23:26:57 +01:00 |
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Emil J. Tywoniak
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ff9cd0eed7
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Makefile: test target requires unit-test, add vanilla-test for old test target
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2026-02-09 23:21:24 +01:00 |
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Gus Smith
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b04948a8cd
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Simplify test
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2026-02-09 09:38:45 -08:00 |
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Gus Smith
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6f6fa49d3c
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Typo
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2026-02-09 09:05:56 -08:00 |
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Gus Smith
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1502e23371
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Set solver from scratchpad or command line
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2026-02-06 19:26:32 -08:00 |
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Gus Smith
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b2f9ac4fb5
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Check for dimacs nullptr on file creation+fn call
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2026-02-06 18:18:03 -08:00 |
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Gus Smith
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2bb352a861
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Missing newline
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2026-02-06 17:45:00 -08:00 |
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Gus Smith
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f062a0c8d6
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Typo
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2026-02-06 17:26:08 -08:00 |
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Robert O'Callahan
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34f8582725
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Sanitize ABC global and per-run temporary directory names in logs
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2026-02-07 12:12:13 +13:00 |
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Emil J
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1717fa0180
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Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift
opt_expr: fix const lhs of $pow to $shl
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2026-02-05 13:09:01 +01:00 |
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github-actions[bot]
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0640a5904b
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Bump version
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2026-02-05 00:33:25 +00:00 |
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Emil J
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8bbde80e02
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Merge pull request #5631 from rocallahan/cleanup-compare-signals
Clean up `compare_signals()` in `opt_clean`
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2026-02-04 17:45:05 +01:00 |
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Emil J
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2aa0e1d009
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Merge pull request #5629 from rocallahan/remove-zero-wires
Avoid scanning entire module in `Module::remove()` if there are no wires to remove
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2026-02-04 17:44:24 +01:00 |
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Emil J
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992e64342c
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Merge pull request #5621 from rocallahan/remove-opt-sort
Remove `Design::sort()` calls from optimization passes
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2026-02-04 16:55:56 +01:00 |
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Miodrag Milanović
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776b4d06a6
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Merge pull request #5669 from YosysHQ/release/v0.62
Release version 0.62
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2026-02-04 08:55:31 +01:00 |
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Miodrag Milanovic
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ddfa34d743
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Next dev cycle
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2026-02-04 08:54:38 +01:00 |
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Robert O'Callahan
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7326bb7d66
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Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE
(cherry picked from commit 5054fd17d7)
v0.62
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2026-02-04 17:19:10 +13:00 |
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Gus Smith
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3f01d7a33a
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Add test
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2026-02-03 14:41:08 -08:00 |
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Jeppe Johansen
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44afd4bbdd
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Add support for subtraction in preadder
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2026-02-03 08:31:01 -08:00 |
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Miodrag Milanovic
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fc11754557
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Release version 0.62
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2026-02-03 12:09:24 +01:00 |
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Emil J. Tywoniak
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3bfeaee8ca
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opt_expr: fix const lhs of $pow to $shl
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2026-02-03 11:59:00 +01:00 |
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Miodrag Milanović
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6dbe03f0f5
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Merge pull request #5667 from Logikable/vhdl
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
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2026-02-03 07:59:52 +01:00 |
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github-actions[bot]
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153ddc0c84
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Bump version
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2026-02-03 00:33:37 +00:00 |
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Sean Luchen
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224549fb88
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Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
Signed-off-by: Sean Luchen <seanluchen@google.com>
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2026-02-02 15:26:03 -08:00 |
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KrystalDelusion
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414b1b6019
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Merge pull request #5651 from rocallahan/abc-error-nonfatal
Handle ABC nonfatal "Error:" messages
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2026-02-03 08:55:05 +13:00 |
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Emil J
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59653da599
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Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass
Add Design::run_pass()
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2026-02-02 19:30:18 +01:00 |
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Miodrag Milanović
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f5c8368f7a
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Merge pull request #5662 from YosysHQ/update_abc
Update ABC as per 2026-02-02
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2026-02-02 13:44:56 +01:00 |
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Miodrag Milanovic
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b88d6588bc
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Update ABC as per 2026-02-02
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2026-02-02 11:25:57 +01:00 |
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Miodrag Milanović
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ac427a79b0
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Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd
Add unistd header for Linux
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2026-01-30 08:17:43 +01:00 |
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Miodrag Milanović
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382b28acbe
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Merge pull request #5648 from YosysHQ/verific_moreopts
verific: fixed -sv2017 option and added ability to set VHDL standard
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2026-01-30 08:17:19 +01:00 |
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Robert O'Callahan
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9c56c93632
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Add missing newlines to some 'log_error's
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2026-01-30 01:52:19 +00:00 |
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Robert O'Callahan
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6af1b5b19c
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Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal
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2026-01-30 01:52:19 +00:00 |
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github-actions[bot]
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106f289e31
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Bump version
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2026-01-30 00:30:58 +00:00 |
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KrystalDelusion
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5a4ad6a6d0
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Merge pull request #5640 from YosysHQ/krys/fix_mod.py
Don't use `module mod_name(...)` style in cell libs
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2026-01-30 11:40:07 +13:00 |
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Emil J
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a68fee1115
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Merge pull request #5646 from rocallahan/debug-design_equal
Dump module details when `design_equal` fails
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2026-01-29 18:57:24 +01:00 |
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Natalia
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61b1c3c75a
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use run_pass in ecp5 add/sub test
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2026-01-29 02:42:23 -08:00 |
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Natalia
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7439d2489e
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add assertion to run_pass test
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2026-01-29 02:23:07 -08:00 |
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Miodrag Milanovic
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b70f527c67
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verific: fixed -sv2017 option and added ability to set VHDL standard if applicable
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2026-01-29 10:32:30 +01:00 |
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Miodrag Milanović
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6ba8f3dc19
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Merge pull request #5647 from YosysHQ/update_abc
ABC update (MINGW fix)
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2026-01-29 10:12:25 +01:00 |
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Miodrag Milanović
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43db5c9488
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Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl
Upstream verific mixed sv vhdl
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2026-01-29 10:12:09 +01:00 |
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Miodrag Milanovic
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6007b68e9c
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ABC update (MINGW fix)
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2026-01-29 09:30:12 +01:00 |
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Natalia
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8d504ecb48
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verific: use MFCU for SV file list
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2026-01-29 00:03:28 -08:00 |
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Natalia
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b6c148f84a
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tests/verific: ensure mixed -f requires VHDL unit
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2026-01-28 22:46:10 -08:00 |
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github-actions[bot]
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1f6a13dac7
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Bump version
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2026-01-29 00:31:03 +00:00 |
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Robert O'Callahan
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139c38ecfa
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Dump module details when design_equal fails
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2026-01-28 18:32:12 +00:00 |
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