Emil J. Tywoniak
68bb5c6b94
signorm: disable in passes that use swap_names
2026-05-22 18:37:58 +02:00
Emil J. Tywoniak
07628a4042
synth_ice40: always read abc9 model to understand port direction
2026-05-22 18:37:13 +02:00
Miodrag Milanovic
75dcbe03c6
Convert RTLIL::unescape_id of IdString to unescape()
2026-05-16 19:49:45 +02:00
Miodrag Milanovic
8bbc3c359c
Remove id2cstr uses in our code base
2026-05-16 19:49:45 +02:00
Miodrag Milanovic
965a3e67f0
Remove pmgen related users of log_id
2026-05-14 17:28:10 +02:00
Miodrag Milanovic
4a7878b17f
Fixing couple more conversion errors
2026-05-14 15:58:58 +02:00
Miodrag Milanovic
58df27ce7c
Refactor uses of log_id in pgm files
2026-05-14 12:21:32 +02:00
Codexplorer
e41b969da2
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
Lofty
ab316c14d2
Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5
...
abc_new: integration testing via synth_gatemate
2026-05-06 13:40:15 +00:00
Lofty
fecea911ff
synth_gatemate: add -abc_new option
2026-05-06 14:02:48 +01:00
nella
fff034d2f8
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
nella
16b893bd88
Add check before flatten in synth.
2026-05-04 19:05:00 +02:00
Ethan Mahintorabi
805c302411
simplemap: Moves $pmux mapping from techmap.v to simple map
...
This Fixes the slow downs I observed in techmap.v, which we
attempted to fix via the simplify ast.h route originally. This
turned out to be rather complex though.
By moving $pmux to simplemap we can just avoid that code. My
test case now runs in 310s which is 40s faster than the baseline
change.
B:507898959
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com >
2026-04-29 21:20:39 +00:00
Lofty
5197b9c8ce
Merge pull request #5833 from ghaworth/fix-sdp-dipbdip-typo
...
Fix RAMB36E1/E2 SDP parity port mapping typo
2026-04-25 08:41:31 +00:00
Emil J
2dc69a7578
Merge pull request #5828 from YosysHQ/emil/bash-no-fhs
...
Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash
2026-04-23 15:47:57 +00:00
Emil J. Tywoniak
14d0138d0c
Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh
2026-04-23 15:55:11 +02:00
George Haworth
aba5b279c6
Fix RAMB36E1/E2 SDP parity port mapping typo
...
DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never
matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN
condition on the line above. This caused data bits 68-69 to be
silently overwritten with copies of bits 64-65 on every write.
Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu
(RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2
equivalents correctly use == 36.
2026-04-18 19:10:18 +03:00
Emil J. Tywoniak
3e45f9729e
fix $specrule port naming
2026-04-13 22:34:46 +02:00
nella
fc71719e6e
Rename csa_tree to arith_tree.
2026-04-13 12:48:05 +02:00
nella
0f61ba5299
Move csa after alumacc.
2026-04-13 12:48:05 +02:00
nella
b64b75db7a
Add csa to synth.
2026-04-13 12:48:05 +02:00
Emil J
86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef
...
Undefine set&reset behavior of $dffsr
2026-04-08 14:22:34 +00:00
Miodrag Milanović
cc915b4c76
Merge pull request #5717 from zaun/latch-support
...
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
2026-03-23 16:51:30 +00:00
Emil J. Tywoniak
0e7f7c826d
simcells: $dffsr and derivatives undefine S&R in logic tables
2026-03-19 19:27:30 +01:00
Lofty
c4cc53a72e
synth: fix after abc -fast removal
2026-03-18 17:59:58 +01:00
Marcel Jung
49ecb1ac11
fabulous: add frame_config_mux BEls
2026-03-12 16:05:21 +01:00
Lofty
53939bd3ba
synth_quicklogic: fix small multiplier inference
2026-03-11 11:14:09 +00:00
Lofty
050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices
...
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
2026-03-06 08:57:59 +00:00
Miodrag Milanovic
52533b0d1c
Update opt_lut_ins and stat for analogdevices and remove ecp5
2026-03-06 09:10:36 +01:00
Justin Zaun
d9737acc31
gowin: remove lib_whitebox from latch sim cells
...
Latches are sequential elements and don't need lib_whitebox.
2026-03-05 16:04:23 +01:00
Justin Zaun
9288889e20
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
...
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
2026-03-05 16:04:23 +01:00
Lofty
da83c93673
analogdevices: fix SHIFTX name
2026-03-05 05:37:13 +00:00
Lofty
f3efa51b3e
analogdevices: fix SHREG name
2026-03-05 05:37:13 +00:00
Lofty
e2e8245be9
analogdevices: fix MUXF78 name
2026-03-05 05:37:13 +00:00
Lofty
c747466a7a
analogdevices: update missed T40LP timings
2026-03-05 05:37:13 +00:00
Lofty
91740645a9
analogdevices: update T40LP timings
2026-03-05 05:37:13 +00:00
Lofty
709746b184
analogdevices: update T16FFC timings
2026-03-05 05:37:13 +00:00
Lofty
cd60dd4912
synth_analogdevices: update timing model and tests
2026-03-05 05:37:13 +00:00
Lofty
241db706e1
analogdevices: double LUT RAM cost
2026-03-05 05:37:13 +00:00
Lofty
3592d42d3b
analogdevices: ignore $assert cells
2026-03-05 05:37:13 +00:00
Krystine Sherwin
f06018306d
analogdevices: Fixing up bram
...
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
2026-03-05 05:37:13 +00:00
Krystine Sherwin
95ef0cd788
analogdevices: Add BRAM options
...
Enable `-force-params`, and tidy up lutram mapping too.
2026-03-05 05:37:13 +00:00
Lofty
8a09cc5463
analogdevices: LUT RAM only on positive edge
2026-03-05 05:37:13 +00:00
Lofty
dea8c275ff
analogdevices: DSP tweaks
2026-03-05 05:37:12 +00:00
Lofty
39cb61615f
analogdevices: DSP inference
2026-03-05 05:37:12 +00:00
Lofty
891b89f60d
analogdevices: remove cells_xtra
2026-03-05 05:37:12 +00:00
Lofty
4954fc980f
analogdevices: timings for t40lp
2026-03-05 05:37:12 +00:00
Lofty
2c3876671b
analogdevices: use single tech param
2026-03-05 05:37:12 +00:00
Lofty
0a2b6a4f21
analogdevices: expreso does not care about clock buffers
2026-03-05 05:37:12 +00:00
Lofty
6ee0bfa913
analogdevices: prepare for t40lp timings
2026-03-05 05:37:12 +00:00
