Emil J. Tywoniak
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bd437f207f
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abstract: fix test signorm
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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4f665d6efc
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signorm: disable passes that use rewrite_sigspecs
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6447a39c0c
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aiger: ignore $input_port
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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8267dee75a
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check: stitch info about $connect ports together for driver analysis
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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b42136aa8c
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signorm: remove $input cells when leaving
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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5c5df513d1
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abstract: skip $input_port cells
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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dad6277a25
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flatten: skip $input_port cells in template module
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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d541def612
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signorm: skip const when fixing fanout
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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68bb5c6b94
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signorm: disable in passes that use swap_names
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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4d2a6f2b7a
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opt_expr: fix invert_map
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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422a505435
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satgen: support $connect
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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fb03a34277
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rtlil: add dump_sigmap for hacky signorm debugging
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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b859080ef2
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techmap: disable signorm more
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6575e7f1df
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techmap: disable signorm
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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2f7d0913fc
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opt_hier: disable signorm
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2026-05-22 18:37:58 +02:00 |
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Emil J. Tywoniak
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6b06869242
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timinginfo: disable output wire check due to signorm
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2026-05-22 18:37:56 +02:00 |
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Emil J. Tywoniak
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6d08c53429
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rtlil: forbid rewrite_sigspecs in signorm
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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bb2d6f0e2a
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opt_merge_inc: re add initvals deletion
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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07628a4042
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synth_ice40: always read abc9 model to understand port direction
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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5b6b11dd44
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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80a440ed2d
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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69c9f3e619
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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9d86a6636c
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wreduce: fixup initvals after setPort
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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e5266d0fbc
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ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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3dc45005f2
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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af48c1cdfb
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rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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80ca3174ea
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bug2920: disable
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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e6515cfd93
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rtlil_bufnorm: fix cell deletion deferral bug
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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28013eccbc
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tests: adjust to input_port and init behavior (sketchy)
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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dcc4cbea2f
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check: don't fail on $input_port
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2026-05-22 18:37:13 +02:00 |
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Emil J. Tywoniak
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8c4816c802
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mem: fix signorm cell type morph
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2026-05-22 18:37:13 +02:00 |
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Jannis Harder
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423c8be71b
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WIP half broken snapshot
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2026-05-22 18:37:11 +02:00 |
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Jannis Harder
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30505c2cd6
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WIP remove dead code
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2026-05-22 18:34:52 +02:00 |
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Miodrag Milanović
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9d0cdb8551
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Merge pull request #5901 from YosysHQ/test_cleanup
Test out-of-tree build support
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2026-05-20 10:55:28 +00:00 |
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Miodrag Milanovic
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4c8e61a52b
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Expose SBY binary location
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2026-05-19 16:08:21 +02:00 |
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Miodrag Milanovic
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07924a3c62
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Use common.mk for sva tests as well
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2026-05-19 15:15:41 +02:00 |
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Miodrag Milanovic
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2b3f4c37f5
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Fix functional tests
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2026-05-19 14:42:08 +02:00 |
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Miodrag Milanovic
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15e09163cd
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Do not use Makefile.conf
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2026-05-19 14:29:06 +02:00 |
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Miodrag Milanovic
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c0779f488a
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Make out of tree build testing possible
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2026-05-19 14:26:07 +02:00 |
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Emil J
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5c6de04467
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Merge pull request #5875 from YosysHQ/emil/threading-fix-no-threads
threading: redirect locks to no-op on single-threaded builds
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2026-05-18 19:22:19 +00:00 |
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Miodrag Milanović
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ffa8618413
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Merge pull request #5896 from YosysHQ/remove_file
Remove file added by mistake
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2026-05-18 15:39:55 +00:00 |
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Miodrag Milanovic
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2159a0e634
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Remove file added by mistake
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2026-05-18 17:00:16 +02:00 |
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Emil J. Tywoniak
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0c2786be1f
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threading: make no-op locks specialized to Mutex instead of templates
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2026-05-18 16:26:14 +02:00 |
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Emil J. Tywoniak
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1c831aa50d
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threading: whitespace
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2026-05-18 16:26:14 +02:00 |
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Emil J. Tywoniak
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d322e2fbe0
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threading: redirect locks to no-op when ENABLE_THREADS=0 or undefined YOSYS_ENABLE_THREADS
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2026-05-18 16:14:01 +02:00 |
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Miodrag Milanović
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7bcda9d304
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Merge pull request #5893 from YosysHQ/update_log
Log infrastructure cleanup
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2026-05-18 11:10:11 +00:00 |
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Miodrag Milanović
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8b68ac04f7
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Merge pull request #5890 from strophy/fix-aiger-tests-abcexternal
Fix aiger tests when ABCEXTERNAL is set
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2026-05-18 07:59:17 +00:00 |
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Miodrag Milanovic
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35d13e1c32
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Update documentation/demos based on cleanup
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2026-05-18 09:13:46 +02:00 |
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Miodrag Milanovic
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4a4c3a3be6
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Make better validation
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2026-05-18 08:50:38 +02:00 |
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Miodrag Milanovic
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ef092e1f15
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Include conf so individual test running works
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2026-05-18 08:50:20 +02:00 |
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