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Mono Color

• 20a465e9f2 satgen: fix flip flop clock undef Emil J. Tywoniak 2026-02-04 15:38:12 +01:00
• 50db1f428d dff2ff: remove invalid test Emil J. Tywoniak 2026-02-03 21:33:44 +01:00
• 1561834bae satgen: fix flip flop clock Emil J. Tywoniak 2026-01-30 19:04:09 +01:00
• 34f8582725 Sanitize ABC global and per-run temporary directory names in logs Robert O'Callahan 2026-02-07 12:12:13 +13:00
• 1717fa0180 Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift Emil J 2026-02-05 13:09:01 +01:00
• 0640a5904b Bump version github-actions[bot] 2026-02-05 00:33:25 +00:00
• 8bbde80e02 Merge pull request #5631 from rocallahan/cleanup-compare-signals Emil J 2026-02-04 17:45:05 +01:00
• 2aa0e1d009 Merge pull request #5629 from rocallahan/remove-zero-wires Emil J 2026-02-04 17:44:24 +01:00
• 992e64342c Merge pull request #5621 from rocallahan/remove-opt-sort Emil J 2026-02-04 16:55:56 +01:00
• 776b4d06a6 Merge pull request #5669 from YosysHQ/release/v0.62 Miodrag Milanović 2026-02-04 08:55:31 +01:00
• ddfa34d743 Next dev cycle Miodrag Milanovic 2026-02-04 08:54:38 +01:00
• 7326bb7d66 Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE v0.62 Robert O'Callahan 2026-02-03 22:47:20 +00:00
• 3f01d7a33a Add test Gus Smith 2026-02-03 14:41:08 -08:00
• 91b226b4d4 specify: fix test Emil J. Tywoniak 2026-02-03 18:40:32 +01:00
• ed53ff2f49 equiv_simple, equiv_induct: fix config Emil J. Tywoniak 2026-02-03 18:37:39 +01:00
• c768e55983 ice40: fix dsp_const test Emil J. Tywoniak 2026-02-03 18:10:02 +01:00
• 2efd0247a1 opt_hier: fix test Emil J. Tywoniak 2026-02-03 18:09:51 +01:00
• d199195785 satgen: cover $input_port Emil J. Tywoniak 2026-02-03 18:00:45 +01:00
• 8d1c1faf82 equiv_simple, equiv_induct: error by default on missing model, add -ignore-unknown-cells Emil J. Tywoniak 2026-02-03 17:59:31 +01:00
• 8e73e2a306 sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency Emil J. Tywoniak 2026-02-03 17:56:10 +01:00
• 000be270ca equiv_simple, equiv_induct: refactor Emil J. Tywoniak 2026-02-03 17:54:46 +01:00
• 44afd4bbdd Add support for subtraction in preadder Jeppe Johansen 2022-08-24 18:31:45 +02:00
• fc11754557 Release version 0.62 Miodrag Milanovic 2026-02-03 12:09:24 +01:00
• 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl Emil J. Tywoniak 2026-02-02 19:09:30 +01:00
• 6dbe03f0f5 Merge pull request #5667 from Logikable/vhdl Miodrag Milanović 2026-02-03 07:59:52 +01:00
• 153ddc0c84 Bump version github-actions[bot] 2026-02-03 00:33:37 +00:00
• 224549fb88 Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. Sean Luchen 2026-02-02 15:26:03 -08:00
• 414b1b6019 Merge pull request #5651 from rocallahan/abc-error-nonfatal KrystalDelusion 2026-02-03 08:55:05 +13:00
• 59653da599 Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass Emil J 2026-02-02 19:30:18 +01:00
• f5c8368f7a Merge pull request #5662 from YosysHQ/update_abc Miodrag Milanović 2026-02-02 13:44:56 +01:00
• b88d6588bc Update ABC as per 2026-02-02 Miodrag Milanovic 2026-02-02 11:25:57 +01:00
• ac427a79b0 Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd Miodrag Milanović 2026-01-30 08:17:43 +01:00
• 382b28acbe Merge pull request #5648 from YosysHQ/verific_moreopts Miodrag Milanović 2026-01-30 08:17:19 +01:00
• af93a0cfc9 Docs: Initial split of documenting.rst docs-preview-contributing_help Krystine Sherwin 2026-01-30 17:40:46 +13:00
• 9c56c93632 Add missing newlines to some 'log_error's Robert O'Callahan 2026-01-29 18:47:42 +00:00
• 6af1b5b19c Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal Robert O'Callahan 2026-01-29 18:47:12 +00:00
• 106f289e31 Bump version github-actions[bot] 2026-01-30 00:30:58 +00:00
• 0b41bdab66 documenting.rst: Negatives are hard Krystine Sherwin 2026-01-30 12:24:21 +13:00
• 5a4ad6a6d0 Merge pull request #5640 from YosysHQ/krys/fix_mod.py KrystalDelusion 2026-01-30 11:40:07 +13:00
• a68fee1115 Merge pull request #5646 from rocallahan/debug-design_equal Emil J 2026-01-29 18:57:24 +01:00
• 61b1c3c75a use run_pass in ecp5 add/sub test Natalia 2026-01-29 02:42:23 -08:00
• 7439d2489e add assertion to run_pass test Natalia 2026-01-29 02:20:50 -08:00
• b70f527c67 verific: fixed -sv2017 option and added ability to set VHDL standard if applicable Miodrag Milanovic 2026-01-29 10:32:30 +01:00
• 6ba8f3dc19 Merge pull request #5647 from YosysHQ/update_abc Miodrag Milanović 2026-01-29 10:12:25 +01:00
• 43db5c9488 Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl Miodrag Milanović 2026-01-29 10:12:09 +01:00
• 6007b68e9c ABC update (MINGW fix) Miodrag Milanovic 2026-01-29 09:30:12 +01:00
• 8d504ecb48 verific: use MFCU for SV file list Natalia 2026-01-29 00:03:28 -08:00
• b6c148f84a tests/verific: ensure mixed -f requires VHDL unit Natalia 2026-01-28 22:46:10 -08:00
• 1f6a13dac7 Bump version github-actions[bot] 2026-01-29 00:31:03 +00:00
• 139c38ecfa Dump module details when design_equal fails Robert O'Callahan 2026-01-28 18:22:12 +00:00
• 8f6c4d40e4 Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite nella 2026-01-28 14:41:40 +01:00
• 5a64fe2d91 tests/verific: assert module count explicitly Natalia 2026-01-28 04:21:13 -08:00
• 8c2ef89732 tests/verific: import mixed -f list with -all Natalia 2026-01-28 04:13:04 -08:00
• 74c601db0f tests/verific: add mixed -f list case Natalia 2026-01-28 03:55:42 -08:00
• 6a6e5f0f54 linux_perf: only include unistd on Linux Natalia 2026-01-28 03:44:33 -08:00
• 188082551a verific: only use MFCU when VHDL present Natalia 2026-01-28 03:37:08 -08:00
• fc2b7c317f linux_perf: include unistd for POSIX I/O Natalia 2026-01-28 03:14:20 -08:00
• 75008b70e5 Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help Emil J 2026-01-28 11:06:08 +01:00
• 97366933b3 Merge pull request #5643 from YosysHQ/update_abc Miodrag Milanović 2026-01-28 10:21:08 +01:00
• fdff3dac2b Update ABC as per 2026-01-28 Miodrag Milanovic 2026-01-28 09:38:33 +01:00
• 8ed7ac04d8 linux_perf.cc: Fix overlength codeblock Krystine Sherwin 2026-01-28 08:17:50 +13:00
• 4031310ebb linux_perf.cc: Use formatted_help Krystine Sherwin 2026-01-28 08:10:31 +13:00
• aaebce7adc log_help: Don't reformat codeblocks Krystine Sherwin 2026-01-14 07:39:45 +13:00
• c3ffb48a6b Add and use fix_mod.py Krystine Sherwin 2026-01-28 07:45:58 +13:00
• 33e4b1d97f Bump version github-actions[bot] 2026-01-27 00:28:42 +00:00
• 09ceadfde7 Merge pull request #4269 from povik/icells_not_derived Gus Smith 2026-01-26 14:48:40 -08:00
• 5b10c7f3c6 Merge pull request #4928 from XutaxKamay/main Emil J 2026-01-26 23:30:11 +01:00
• ef3b2b0380 linux_perf: mark internal, fix help formatting Emil J. Tywoniak 2026-01-26 22:59:20 +01:00
• a3c9716f18 OptDff fix unit tests. nella 2026-01-26 22:35:25 +01:00
• 9367090763 OptDff more accurate ctrl/pattern desc. nella 2026-01-26 22:19:36 +01:00
• 5803461c24 opt_dff pattern extraction. nella 2026-01-26 22:10:10 +01:00
• 29a9e42b64 Merge pull request #5628 from rocallahan/linux-perf-ctl Emil J 2026-01-26 19:32:55 +01:00
• 8576055dea Fix tests. nella 2026-01-26 18:41:41 +01:00
• 673c8d1ae7 Merge pull request #5615 from rocallahan/remove-used-signals-updates Emil J 2026-01-26 15:47:25 +01:00
• a75e0b2e92 opt_dff minor cleanup, added tests for comp var. nella 2026-01-26 14:24:01 +01:00
• 383daa1eb3 proc_mux: include switch expression location in $eq src Emil J. Tywoniak 2026-01-26 12:02:09 +01:00
• 53585db9f7 kernel: add SwitchRule signal_src Emil J. Tywoniak 2026-01-26 11:59:39 +01:00
• 85a17b0366 docs: workaround for warning from dump Emil J. Tywoniak 2025-12-12 10:18:28 +01:00
• a24c260998 proc_mux, genrtlil: make use of case_src for better case condition vs block tracking Emil J. Tywoniak 2025-12-11 00:45:30 +01:00
• a217a5c716 rtlil: add case_src to CaseRule Emil J. Tywoniak 2025-12-11 00:44:52 +01:00
• 502ba3734b proc_mux: copy switch src to _CMP wire Emil J. Tywoniak 2025-12-10 21:35:03 +01:00
• da65a18f39 proc_mux: copy mux src to Y port Emil J. Tywoniak 2025-12-10 18:46:44 +01:00
• ee800087e8 proc_mux: add comments Emil J. Tywoniak 2025-11-15 01:58:16 +01:00
• b3aea1b5d2 proc_mux: optimize source map locality for index density Emil J. Tywoniak 2025-11-15 01:04:30 +01:00
• 4072bcfd0b proc_dff: add wire src attributes to dff cells Emil J. Tywoniak 2025-11-07 21:32:09 +01:00
• f4a69805ae verific: use SyncActions Emil J. Tywoniak 2025-11-07 18:23:47 +01:00
• 469083dcaa proc_mux: default to case src when action src is missing Emil J. Tywoniak 2025-11-02 12:41:55 +01:00
• a2e8e352b6 proc_mux: add src test Emil J. Tywoniak 2025-11-02 11:10:08 +01:00
• 985e98935f docs: word_mux grammar Emil J. Tywoniak 2025-11-02 11:09:14 +01:00
• 778a667a91 proc_mux: refactor Emil J. Tywoniak 2025-11-02 11:09:01 +01:00
• cacd584347 proc_mux: emit fused action location src attributes on procmuxes Emil J. Tywoniak 2025-10-30 15:41:46 +01:00
• c36370f227 rtlil: add source tracking to CaseRule actions Emil J. Tywoniak 2025-11-02 11:25:42 +01:00
• 5ec1cc0dec gowin: lower LUT count sensitivity Emil J. Tywoniak 2025-11-02 11:22:48 +01:00
• 7713b5a811 verilog: fix case location Emil J. Tywoniak 2025-11-02 11:22:33 +01:00
• 94a53e08bc rtlil: replace SigSig actions with new type SyncAction Emil J. Tywoniak 2025-11-02 11:22:03 +01:00
• 808ec8c04b gowin: synth_gowin: Add MULT inference for GW1N and GW2A Maxim Kudinov 2026-01-25 22:10:08 +03:00
• f3c87610f5 verific: allow mixed SV/VHDL in -f files nataliakokoromyti 2026-01-24 23:46:45 -08:00
• 32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals. Robert O'Callahan 2026-01-19 02:44:54 +00:00
• 7d53d64a47 Make the call to compare_signals() easier to read. Robert O'Callahan 2026-01-24 01:51:34 +00:00
• 2468b391bf Make compare_signals produce a total order. Robert O'Callahan 2026-01-24 01:48:15 +00:00