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emil/fix-dangling-wiretype-2

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Mono Color

• c9a4feba6a Merge pull request #399 from azonenberg/counter-extraction Clifford Wolf 2017-08-31 17:54:28 +02:00
• 16043b79b6 Merge branch 'counter-extraction' of github.com:azonenberg/yosys into counter-extraction Andrew Zonenberg 2017-08-30 18:16:15 -07:00
• ed1e3ed39b extract_counter: Added optimizations to remove unused high-order bits Andrew Zonenberg 2017-08-30 18:14:22 -07:00
• 06754108fc Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction Andrew Zonenberg 2017-08-30 16:40:41 -07:00
• 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos Andrew Zonenberg 2017-08-30 16:27:18 -07:00
• 71d43cfc08 Merge remote-tracking branch 'upstream/master' Jason Lowdermilk 2017-08-30 11:47:06 -06:00
• 271e8ba7cd fix indent level Jason Lowdermilk 2017-08-30 11:46:41 -06:00
• c0034f51e6 Merge pull request #397 from azonenberg/gpak-libfixes Clifford Wolf 2017-08-30 11:53:44 +02:00
• 8530333439 Add {get,set}_src_attribute() methods on RTLIL::AttrObject Clifford Wolf 2017-08-30 11:39:11 +02:00
• 32c0f1193e Add support for source line tracking through synthesis phase Jason Lowdermilk 2017-08-29 14:46:35 -06:00
• 3fc1b9f3fd Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. Andrew Zonenberg 2017-08-28 22:13:36 -07:00
• 46b01f05bb Refactored extract_counter to be generic vs GreenPAK specific Andrew Zonenberg 2017-08-28 21:48:20 -07:00
• b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass Andrew Zonenberg 2017-08-28 20:52:08 -07:00
• c3145863e7 Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused. Andrew Zonenberg 2017-08-28 09:06:37 -07:00
• 393b18e8e1 Merge branch 'azonenberg-recover-reduce' Clifford Wolf 2017-08-28 19:52:51 +02:00
• 908f34aafc Rename recover_reduce to extract_reduce, fix args handling Clifford Wolf 2017-08-28 19:52:06 +02:00
• 3aad3ed3da Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce Clifford Wolf 2017-08-28 19:46:17 +02:00
• ebbb0e9479 Further improve extract_fa pass Clifford Wolf 2017-08-28 19:43:26 +02:00
• a682800187 Merge pull request #392 from azonenberg/greenpak-portfixes Clifford Wolf 2017-08-28 15:29:58 +02:00
• e62362225c Fixed bug causing GP_SPI model to not synthesize Andrew Zonenberg 2017-08-14 15:32:07 -07:00
• 849b885775 recover_reduce: Update documentation Robert Ou 2017-08-27 02:19:19 -07:00
• 74d0f17fd4 recover_reduce: Reindent using tabs Robert Ou 2017-08-27 02:12:41 -07:00
• 8a5887464c recover_reduce: Rename recover_reduce_core to recover_reduce Robert Ou 2017-08-27 02:01:32 -07:00
• 99dad40ed0 recover_reduce: Add driver script for the $reduce_* recover feature Robert Ou 2017-08-11 02:00:33 -07:00
• 8b7dc792ee recover_reduce_core: Finish implementing the core function Robert Ou 2017-08-11 01:48:22 -07:00
• fa310c98f8 recover_reduce_core: Initial commit Robert Ou 2017-08-11 00:40:31 -07:00
• 68c42f3a19 Don't track , ... contradictions through x/z-bits Clifford Wolf 2017-08-25 16:18:17 +02:00
• db6d78a186 Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr Clifford Wolf 2017-08-25 16:02:15 +02:00
• 86df0fb381 Merge branch 'extract_fa' Clifford Wolf 2017-08-25 13:42:13 +02:00
• 382cc90c65 Further improve extract_fa (seems to be fully functional now) Clifford Wolf 2017-08-25 13:41:54 +02:00
• 0bf612506c Rename "adders" to "extract_fa" Clifford Wolf 2017-08-25 12:04:40 +02:00
• c2d737457a Fix bug in write_smt2 (export logic driving hierarchical cells before exporting regs) Clifford Wolf 2017-08-25 11:44:48 +02:00
• 15cdda7c4b Towards more generic "adder" function extractor Clifford Wolf 2017-08-23 14:20:10 +02:00
• 51cbec7f75 Add experimental adders pass Clifford Wolf 2017-08-22 13:48:55 +02:00
• d3b3dd8e88 Add hashlib support for hashing of pools Clifford Wolf 2017-08-22 13:04:33 +02:00
• bce0bb6e43 Add consteval support for $_ANDNOT_ and $_ORNOT_ Clifford Wolf 2017-08-22 13:04:05 +02:00
• df3e6e1ec9 Remove some dead code from fsm_map Clifford Wolf 2017-08-21 15:02:16 +02:00
• ca53fba44a Rename "singleton" pass to "uniquify" Clifford Wolf 2017-08-20 12:31:50 +02:00
• d38a64b1cf More intuitive handling of "cd .." for singleton modules Clifford Wolf 2017-08-19 00:15:12 +02:00
• bbdf7d9c66 Add "sim -zinit -rstlen" Clifford Wolf 2017-08-18 12:54:17 +02:00
• 35760dd784 Merge branch 'sim' Clifford Wolf 2017-08-18 11:45:15 +02:00
• d30cc60ba9 Add "sim" support for memories Clifford Wolf 2017-08-18 11:44:50 +02:00
• 4ba5bd12c6 Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() Clifford Wolf 2017-08-18 11:40:08 +02:00
• 0be738eaac Add support for assert/assume/cover to "sim" command Clifford Wolf 2017-08-18 10:24:14 +02:00
• 92e4b5aa77 Add writeback mode to "sim" command Clifford Wolf 2017-08-17 15:54:51 +02:00
• 7b4f3f86c3 Improve "sim" command Clifford Wolf 2017-08-17 12:27:08 +02:00
• 864498527a Merge pull request #386 from azonenberg/gpak-counters Clifford Wolf 2017-08-16 15:58:29 +02:00
• 75046aa531 Add "sim" command skeleton Clifford Wolf 2017-08-16 13:05:21 +02:00
• e6eaf487b6 Fixed more issues with GreenPAK counter sim models Andrew Zonenberg 2017-08-15 00:50:31 -07:00
• 3a404be62a Updated PGEN model to have level triggered reset (matches actual hardware behavior Andrew Zonenberg 2017-08-14 17:15:56 -07:00
• e5109847c9 Fixed bug in GP_COUNTx model Andrew Zonenberg 2017-08-14 16:28:59 -07:00
• 66b256d40e Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high Andrew Zonenberg 2017-08-14 16:08:54 -07:00
• e9918365fd Merge branch 'azonenberg-rmports' Clifford Wolf 2017-08-15 11:32:55 +02:00
• 88983f5012 Mostly coding style related fixes in rmports pass Clifford Wolf 2017-08-15 11:32:35 +02:00
• 9fe6bc48a9 Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports Clifford Wolf 2017-08-15 11:19:55 +02:00
• 2cf0b5c157 Merge pull request #381 from azonenberg/countfix Clifford Wolf 2017-08-14 21:47:26 +02:00
• 6d371f06ab Merge pull request #383 from azonenberg/abcfnames Clifford Wolf 2017-08-14 21:46:17 +02:00
• 76efbcc15f Merge pull request #382 from azonenberg/jsoniofix Clifford Wolf 2017-08-14 21:45:54 +02:00
• 237b482b92 Merge pull request #384 from azonenberg/crtechlib Clifford Wolf 2017-08-14 21:45:29 +02:00
• 78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs Robert Ou 2017-08-07 04:01:18 -07:00
• 1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v Robert Ou 2017-08-01 11:58:01 -07:00
• 9a64ba3338 abc: Allow +/ filenames in the abc command Robert Ou 2017-08-10 21:10:07 -07:00
• 366ce87cff json: Parse inout correctly rather than as an output Robert Ou 2017-08-07 13:37:01 -07:00
• 15e41d6363 rmports: Now remove ports from cell instances if we optimized them out of that cell Andrew Zonenberg 2017-08-14 11:44:05 -07:00
• 0ee27d0226 ProcessModule is no longer virtual (why was it in the first place?) Andrew Zonenberg 2017-08-14 11:18:09 -07:00
• bd2ac68769 rmports now works on all modules in the design, not just the top. Andrew Zonenberg 2017-08-14 11:16:44 -07:00
• d5e5bbad86 Updated Makefile to reflect opt_rmports being renamed to rmports Andrew Zonenberg 2017-08-14 11:04:56 -07:00
• 1a6a23f91a Renamed opt_rmports pass to rmports Andrew Zonenberg 2017-08-14 11:00:18 -07:00
• 348acbd968 Fixed typo in GP_COUNT8 sim model Andrew Zonenberg 2017-08-11 16:55:31 -07:00
• c205d571df Fixed typo in error message Andrew Zonenberg 2017-08-07 20:46:00 -07:00
• 0a6c702c41 Changed LEVEL resets for GP_COUNTx to be properly synthesizeable Andrew Zonenberg 2017-08-07 20:42:19 -07:00
• 9f3dc59ffe Changed LEVEL resets to be edge triggered anyway Andrew Zonenberg 2017-08-07 20:33:08 -07:00
• b049ead042 Added level-triggered reset support to GP_COUNTx simulation models Andrew Zonenberg 2017-08-07 20:29:05 -07:00
• ac75524f69 Fixed undeclared "count" in GP_COUNT8_ADV Andrew Zonenberg 2017-08-07 20:21:55 -07:00
• db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV Andrew Zonenberg 2017-08-07 20:21:18 -07:00
• 3618ca2218 Fixed typo in last commit Andrew Zonenberg 2017-08-07 20:20:17 -07:00
• 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. Andrew Zonenberg 2017-08-07 20:19:17 -07:00
• 4504dd78e9 Fixed typo in COUNT8 model Andrew Zonenberg 2017-08-07 15:49:30 -07:00
• 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays Andrew Zonenberg 2017-08-06 08:40:23 -07:00
• f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 Andrew Zonenberg 2017-08-05 17:33:44 -07:00
• fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital Andrew Zonenberg 2017-08-05 16:33:24 -07:00
• 1bb150c231 Improved handling of constant connections in opt_rmports Andrew Zonenberg 2017-08-11 16:47:07 -07:00
• 2877d5e504 Fixed handling of cell ports that aren't wires Andrew Zonenberg 2017-08-11 16:16:25 -07:00
• 3dd7f42e2b opt_rmports: Fixed incorrect handling of multi-bit nets Andrew Zonenberg 2017-08-11 15:07:27 -07:00
• 66aac06eee Removed commented out debug code Andrew Zonenberg 2017-08-11 13:46:01 -07:00
• cca3cb5fbb Added opt_rmports pass (remove unconnected ports from top-level modules) Andrew Zonenberg 2017-08-11 13:40:37 -07:00
• 007f29b9c2 Add support for set-reset cell variants to opt_rmdff Clifford Wolf 2017-08-09 13:29:52 +02:00
• 159701962a Auto-detect JSON front-end Clifford Wolf 2017-08-09 13:28:52 +02:00
• c4a7958f70 Add handling of constant reset signals to opt_rmdff Clifford Wolf 2017-08-06 13:27:18 +02:00
• 48b2b376d0 Add "yosys-smtbmc --smtc-init --smtc-top --noinit" Clifford Wolf 2017-08-04 17:09:08 +02:00
• 1dc921d9a1 Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags" Clifford Wolf 2017-08-04 11:24:58 +02:00
• 5c09f24e48 Fix typo in "abc" pass help message Clifford Wolf 2017-07-29 16:21:58 +02:00
• 15073790bf Add merging of "past FFs" to verific importer Clifford Wolf 2017-07-29 00:07:02 +02:00
• e7d1277a2c Add consolidation of init attributes to opt_clean, some opt_clean log fixes Clifford Wolf 2017-07-28 23:11:52 +02:00
• d4b9602cbd Add minimal support for PSL in VHDL via Verific Clifford Wolf 2017-07-28 17:37:09 +02:00
• 4cf890dac1 Add simple VHDL+PSL example Clifford Wolf 2017-07-28 15:33:30 +02:00
• 5a828fff34 Improve Verific HDL language options Clifford Wolf 2017-07-28 15:32:54 +02:00
• acd6cfaf67 Fix handling of non-user-declared Verific netbus Clifford Wolf 2017-07-28 11:31:27 +02:00
• c1cfca8f54 Improve Verific SVA importer Clifford Wolf 2017-07-27 14:05:09 +02:00
• 877ff1f75e Add counter.sv SVA test Clifford Wolf 2017-07-27 12:37:16 +02:00