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emil/fix-dangling-wiretype-2

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Mono Color

• 2336d5508b Add log_warning_noprefix() API, Use for Verific warnings and errors Clifford Wolf 2017-07-27 12:17:04 +02:00
• d9641621d9 Add "verific -import -n" and "verific -import -nosva" Clifford Wolf 2017-07-27 11:54:45 +02:00
• b24f737759 Improve SVA tests, add Makefile and scripts Clifford Wolf 2017-07-27 11:42:05 +02:00
• 90d8329f64 Improve Verific SVA import: negedge and $past Clifford Wolf 2017-07-27 11:40:07 +02:00
• 147ff96ba3 Improve Verific SVA importer Clifford Wolf 2017-07-27 10:39:39 +02:00
• 649bb9374f Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators Clifford Wolf 2017-07-26 18:28:55 +02:00
• 530040ba6f Improve Verific bindings (mostly related to SVA) Clifford Wolf 2017-07-26 18:00:01 +02:00
• abd3b4e8e7 Improve "help verific" message Clifford Wolf 2017-07-25 15:13:22 +02:00
• 6dbe1d4c92 Add "verific -extnets" Clifford Wolf 2017-07-25 14:53:11 +02:00
• 493fedbaf9 Add "using std::get" to yosys.h Clifford Wolf 2017-07-25 14:52:34 +02:00
• c97c92e4ec Improve "verific -all" handling Clifford Wolf 2017-07-25 13:33:25 +02:00
• 41be530c4e Add "verific -import -d <dump_file" Clifford Wolf 2017-07-24 13:57:16 +02:00
• 92d3aad670 Add "verific -import -flatten" and "verific -import -v" Clifford Wolf 2017-07-24 11:29:06 +02:00
• 84f15260b5 Add more SVA test cases for future Verific work Clifford Wolf 2017-07-22 16:35:46 +02:00
• 5be535517c Add "verific -import -k" Clifford Wolf 2017-07-22 16:16:44 +02:00
• b6bd12fade Add error for cell output ports that are connected to constants Clifford Wolf 2017-07-22 15:08:30 +02:00
• 024ba310ec Add some simple SVA test cases for future Verific work Clifford Wolf 2017-07-22 12:31:08 +02:00
• 2785aaffeb Improve docs for verific bindings, add simply sby example Clifford Wolf 2017-07-22 11:58:51 +02:00
• b3bc7068d1 Fix handling of empty cell port assignments (i.e. ignore them) Clifford Wolf 2017-07-21 19:32:31 +02:00
• 36cf18ac4c Fix "read_blif -wideports" handling of cells with wide ports Clifford Wolf 2017-07-21 16:21:04 +02:00
• 26766da343 Add a paragraph about pre-defined macros to read_verilog help message Clifford Wolf 2017-07-21 14:34:53 +02:00
• 3a8f6f0f51 Add verilator support to testbenches generated by yosys-smtbmc Clifford Wolf 2017-07-21 14:33:29 +02:00
• c251e3a576 Change intptr_t to uintptr_t in hashlib.h Clifford Wolf 2017-07-18 17:38:19 +02:00
• dbb2f755c1 Merge pull request #363 from rqou/master Clifford Wolf 2017-07-18 15:21:12 +02:00
• 85d667ca08 makefile: Add the option to use libtermcap Robert Ou 2017-07-17 14:21:59 -07:00
• f0741698fa Fix build warnings for win64 Robert Ou 2017-07-17 12:36:43 -07:00
• c00d8a5b73 Add $alu to list of supported cells for "stat -width" Clifford Wolf 2017-07-14 11:32:49 +02:00
• 10c7709e68 Generate FSM-style testbenches in smtbmc Clifford Wolf 2017-07-12 15:57:04 +02:00
• 4a8c131fa7 Fix the fixed handling of x-bits in EDIF back-end Clifford Wolf 2017-07-11 17:45:29 +02:00
• 479be3cec7 Fix handling of x-bits in EDIF back-end Clifford Wolf 2017-07-11 17:38:19 +02:00
• 9557fd2a36 Add attributes and parameter support to JSON front-end Clifford Wolf 2017-07-10 13:17:38 +02:00
• 8a69759306 Add techlibs/xilinx/lut2lut.v Clifford Wolf 2017-07-10 12:09:05 +02:00
• 4b2d1fe688 Add JSON front-end Clifford Wolf 2017-07-08 16:40:40 +02:00
• 3c693b6561 Change s/asserts/assertions/ in yosys-smtbmc log messages Clifford Wolf 2017-07-07 11:52:25 +02:00
• 8f7404f82c Add "yosys-smtbmc --presat" Clifford Wolf 2017-07-07 02:47:30 +02:00
• 5442554e6f Fix generation of multiple outputs for same AIG node in write_aiger Clifford Wolf 2017-07-05 14:23:54 +02:00
• 37af6294bd Add write_table command Clifford Wolf 2017-07-05 12:13:53 +02:00
• 28039c3063 Add Verific Release information to log Clifford Wolf 2017-07-04 20:01:30 +02:00
• 621787a9e0 Fix some c++ clang compiler errors Clifford Wolf 2017-07-03 19:38:30 +02:00
• 5c1c126374 Apply minor coding style changes to coolrunner2 target Clifford Wolf 2017-07-03 19:35:40 +02:00
• 6afee022ad Merge pull request #352 from rqou/master Clifford Wolf 2017-07-03 19:33:36 +02:00
• 3f863c607a Merge pull request #356 from set-soft/clean-test Clifford Wolf 2017-07-03 19:33:25 +02:00
• d223292aa9 Merge pull request #355 from set-soft/exclude_TBUF_merge Clifford Wolf 2017-07-03 19:31:59 +02:00
• fb30511044 Added the test outputs to the clean target Salvador E. Tropea 2017-07-03 13:33:11 -03:00
• ca23554528 Excluded $_TBUF_ from opt_merge pass Salvador E. Tropea 2017-07-03 13:21:20 -03:00
• 3e0948e16f Remove unneeded delays in smtbmc vlogtb Clifford Wolf 2017-07-03 15:37:17 +02:00
• 287831dca3 Include output ports with constant driver in AIGER output Clifford Wolf 2017-07-03 14:53:17 +02:00
• ea805af6f5 Add "yosys-smtbmc --vlogtb-top" Clifford Wolf 2017-07-01 18:19:23 +02:00
• 0a02cdb93b Fix and_or_buffer optimization in opt_expr for signed operators Clifford Wolf 2017-07-01 16:05:26 +02:00
• 7d2fb6e2fc Fix smtbmc vlogtb bug in $anyseq handling Clifford Wolf 2017-07-01 02:13:32 +02:00
• 0f217080cf Add "design -import" Clifford Wolf 2017-06-30 18:52:52 +02:00
• 8952bd6f45 Add chtype command Clifford Wolf 2017-06-30 17:57:34 +02:00
• 18c030a8c9 Add $tribuf to opt_merge blacklist Clifford Wolf 2017-06-30 17:44:44 +02:00
• 5b95901a1e Merge pull request #353 from azonenberg/master Clifford Wolf 2017-06-27 19:18:32 +02:00
• b102c0e254 coolrunner2: Add a few more primitives Robert Ou 2017-06-25 23:56:16 -07:00
• 36b75dfcb7 coolrunner2: Initial mapping of latches Robert Ou 2017-06-25 20:58:45 -07:00
• 4af5baab21 coolrunner2: Initial mapping of DFFs Robert Ou 2017-06-25 20:16:43 -07:00
• 1eb5dee799 coolrunner2: Remove redundant INVERT_PTC Robert Ou 2017-06-25 02:56:45 -07:00
• ffff001008 coolrunner2: Remove debug prints Robert Ou 2017-06-25 02:44:03 -07:00
• 5798105d47 coolrunner2: Correctly handle $_NOT_ after $sop Robert Ou 2017-06-25 02:42:36 -07:00
• 908ce3fdce coolrunner2: Also construct the XOR cell in the macrocell Robert Ou 2017-06-25 02:20:42 -07:00
• a64b56648d coolrunner2: Initial techmapping for $sop Robert Ou 2017-06-24 08:51:24 -07:00
• cbdddc3af9 greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included Andrew Zonenberg 2017-06-24 14:54:07 -07:00
• 6e0fb889fa coolrunner2: Initial commit Robert Ou 2017-06-24 06:59:20 -07:00
• 155a80dfb7 Fix handling of init values in "abc -dff" and "abc -clk" Clifford Wolf 2017-06-20 15:32:23 +02:00
• 1f517d2b96 Fix history namespace collision Clifford Wolf 2017-06-20 05:26:12 +02:00
• c0ca99483c Store command history when terminating with an error Clifford Wolf 2017-06-20 04:41:58 +02:00
• f6421c83a2 Switched abc "clock domain not found" error to log_cmd_error() Clifford Wolf 2017-06-20 04:22:34 +02:00
• 8f8baccfde Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg" Clifford Wolf 2017-06-07 12:30:24 +02:00
• 129984e115 Fix handling of Verilog ~& and ~| operators Clifford Wolf 2017-06-01 12:43:21 +02:00
• 0290b68a44 Update ABC to hg rev efbf7f13ea9e Clifford Wolf 2017-05-31 11:55:37 +02:00
• e7a984a4df Add dff2ff.v techmap file Clifford Wolf 2017-05-31 11:45:58 +02:00
• c365e33fd7 Fix AIGER back-end for multiple symbols per input/latch/output/property Clifford Wolf 2017-05-30 19:09:11 +02:00
• 05df3dbee4 Add "setundef -anyseq" Clifford Wolf 2017-05-28 11:59:05 +02:00
• 9ed4c9d710 Improve write_aiger handling of unconnected nets and constants Clifford Wolf 2017-05-28 11:31:35 +02:00
• d9201b85f3 Change default smt2 solver to yices (Yices 2 has switched its license to GPL) Clifford Wolf 2017-05-27 11:56:01 +02:00
• fad52abf70 Add aliases for common sets of gate types to "abc -g" Clifford Wolf 2017-05-24 11:39:05 +02:00
• dca3b3cd5f Add examples/osu035 Clifford Wolf 2017-05-23 18:38:20 +02:00
• 664ba4d80e Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2017-05-23 18:24:27 +02:00
• e0386d04f5 Merge pull request #346 from azonenberg/master Clifford Wolf 2017-05-23 14:07:30 +02:00
• 184bd148c9 greenpak4_counters: Added support for parallel output from GP_COUNTx cells Andrew Zonenberg 2017-05-22 19:39:55 -07:00
• 2122ae69b3 Add workaround for CBMC bug to SimpleC back-end Clifford Wolf 2017-05-17 21:07:54 +02:00
• 662a047815 Enable readline and tcl in mxe builds Clifford Wolf 2017-05-17 20:46:22 +02:00
• 6934b862d3 Add missing AndnotGate() and OrnotGate() declarations to rtlil.h Clifford Wolf 2017-05-17 19:10:57 +02:00
• 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates Clifford Wolf 2017-05-17 09:08:29 +02:00
• 9f4fbc5e74 Add <modname>_init() function generator to simpleC back-end Clifford Wolf 2017-05-16 19:34:07 +02:00
• 35be567605 Improve simplec back-end Clifford Wolf 2017-05-16 08:50:23 +02:00
• 8d3c706459 Improve simplec back-end Clifford Wolf 2017-05-15 13:21:59 +02:00
• 9c397ea78b Improve simplec back-end Clifford Wolf 2017-05-14 13:14:49 +02:00
• 628daab277 Improve simplec back-end Clifford Wolf 2017-05-13 18:47:31 +02:00
• ef7594ce3d Improve simplec back-end Clifford Wolf 2017-05-12 22:36:53 +02:00
• 7931e1ebb4 Added support for more gate types to simplec back-end Clifford Wolf 2017-05-12 17:42:31 +02:00
• bd4ed19887 Add first draft of simple C back-end Clifford Wolf 2017-05-12 14:13:33 +02:00
• 241dc7dfb4 Update ABC to hg rev e79576e10d72 Clifford Wolf 2017-05-11 10:32:32 +02:00
• 1a4b7c6bfa Fix boolector support in yosys-smtbmc Clifford Wolf 2017-05-08 14:33:22 +02:00
• e91548b33e Add support for localparam in module header Clifford Wolf 2017-04-30 17:20:30 +02:00
• 3bbac5c141 Fix equiv_simple, old behavior now available with "equiv_simple -short" Clifford Wolf 2017-04-28 18:54:53 +02:00
• f0db8ffdbc Add support for `resetall compiler directive Clifford Wolf 2017-04-26 16:09:32 +02:00
• b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example) Clifford Wolf 2017-04-12 16:51:46 +02:00
• 2021ddecb3 Squelch trailing whitespace Larry Doolittle 2017-04-08 20:54:31 -07:00