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emil/fix-dangling-wiretype-2

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Mono Color

• 3928482a3c Add $cover cell type and SVA cover() support Clifford Wolf 2017-02-04 14:14:26 +01:00
• 911c44d164 Add assert/assume support to verific front-end Clifford Wolf 2017-02-04 13:36:00 +01:00
• 249ddbc16c Update ABC to hg rev fe96921e5d50 Clifford Wolf 2017-02-01 11:15:37 +01:00
• 8927e19b13 Update ABC scripts to use "&nf" instead of "map" Clifford Wolf 2017-02-01 11:14:20 +01:00
• c17aab2957 Merge branch 'C-Elegans-opt_compare_pr' Clifford Wolf 2017-01-31 16:21:23 +01:00
• ffbe8d41f3 Fix indenting and log messages in code merged from opt_compare_pr Clifford Wolf 2017-01-31 16:20:56 +01:00
• 19a980277f Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr Clifford Wolf 2017-01-31 15:54:41 +01:00
• 44b47b57e3 use Homebrew only if installed Steffen Vogel 2017-01-31 10:06:06 -03:00
• 7481ba4750 Improve opt_rmdff support for $dlatch cells Clifford Wolf 2017-01-31 10:15:04 +01:00
• a94c3694d7 Refactor and generalize the comparision optimization C-Elegans 2017-01-30 17:52:16 -05:00
• 18ea65ef04 Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" support Clifford Wolf 2017-01-30 11:38:43 +01:00
• fe29869ec5 Add $ff and $_FF_ support to equiv_simple Clifford Wolf 2017-01-30 10:50:38 +01:00
• e54c355b41 Add "yosys-smtbmc --aig-noheader" and AIGER mem init support Clifford Wolf 2017-01-28 15:14:56 +01:00
• 45e10c1c89 Be more conservative with merging large cells into FSMs Clifford Wolf 2017-01-26 09:19:28 +01:00
• 49b8160488 Add warnings for quickly growing FSM table size in fsm_expand Clifford Wolf 2017-01-26 09:01:26 +01:00
• b0a430f601 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2017-01-26 08:59:26 +01:00
• b54972c112 Fix RTLIL::Memory::start_offset initialization Clifford Wolf 2017-01-25 17:00:59 +01:00
• 2fa0fd4a37 Do not use b.as_int() in calculation of bit set C-Elegans 2017-01-21 12:58:26 -05:00
• fea528280b Add "enum" and "typedef" lexer support Clifford Wolf 2017-01-17 17:33:52 +01:00
• 84f9cd0025 Optimize compares to powers of 2 Remove opt_compare and put comparison pass in opt_expr C-Elegans 2017-01-16 10:16:03 -05:00
• 87fe8ab3f2 Merge pull request #293 from thoughtpolice/minor-cleanup Clifford Wolf 2017-01-16 10:25:25 +01:00
• 6781543244 passes/hierarchy: delete some dead code Austin Seipp 2017-01-15 16:39:12 -06:00
• 943389cdd5 Fix issue #269, optimize signed compare with 0 C-Elegans 2017-01-15 09:23:04 -05:00
• 0c83a30f95 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2017-01-15 09:43:15 -08:00
• 78f65f89ff Fix bug in AstNode::mem2reg_as_needed_pass2() Clifford Wolf 2017-01-15 13:52:50 +01:00
• b7cfb7dbd2 Fix $initstate handling bug in yosys-smtbmc Clifford Wolf 2017-01-11 14:14:12 +01:00
• 8953a55cd8 Update ABC to hg id f8cadfe3861f Clifford Wolf 2017-01-11 10:56:27 +01:00
• 8012de40b9 Updated ABC to hg id 38b26a543f1d Clifford Wolf 2017-01-08 11:57:52 +01:00
• ac90de73be Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2017-01-05 06:05:58 -08:00
• 2d32c6c4f6 Fixed handling of local memories in functions Clifford Wolf 2017-01-05 13:18:58 +01:00
• 0cac95ea94 Added "check -initdrv" Clifford Wolf 2017-01-04 18:12:41 +01:00
• 81a9ee2360 Added handling of local memories and error for local decls in unnamed blocks Clifford Wolf 2017-01-04 16:03:04 +01:00
• b9ad91b93e Implicitly set "yosys-smtbmc --noprogress" on windows Clifford Wolf 2017-01-04 15:23:48 +01:00
• 080004b19a Fixed typo in tests/simple/arraycells.v Clifford Wolf 2017-01-04 12:39:01 +01:00
• ed812ea39c Fixed "yosys-smtbmc --noprogress" Clifford Wolf 2017-01-04 12:03:04 +01:00
• dfb461fe52 Added Verilog $rtoi and $itor support Clifford Wolf 2017-01-03 17:40:58 +01:00
• 81bb952e5d Handle "always 1" like "always -1" in .smtc files Clifford Wolf 2017-01-02 20:02:52 +01:00
• babd8dc5b1 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2017-01-01 14:08:16 -08:00
• f0df7dd796 Added cell port resizing to hierarchy pass Clifford Wolf 2017-01-01 22:52:52 +01:00
• 27a626ce98 greenpak4: Added POUT to GP_COUNTx cells Andrew Zonenberg 2017-01-01 00:56:20 -08:00
• a7fb64efe6 Updated ABC to hg id 55cd83f432c0 Clifford Wolf 2016-12-31 21:52:27 +01:00
• 6b2c23c721 Bugfix in RTLIL::SigSpec::remove2() Clifford Wolf 2016-12-31 16:14:42 +01:00
• 7da7a6d1df Updated ABC to hg id 8c6a635f7a20 Clifford Wolf 2016-12-29 12:20:35 +01:00
• 2198948398 Improved write_json help message Clifford Wolf 2016-12-29 12:13:29 +01:00
• 4f5efc3416 Updated ABC to hg id f591c081d5e7 Clifford Wolf 2016-12-26 17:52:38 +01:00
• 4cf3170194 Merge pull request #284 from azonenberg/master Clifford Wolf 2016-12-24 14:28:39 +01:00
• 5ffede5c0e Merge pull request #1 from azonenberg-hk/master Andrew Zonenberg 2016-12-23 12:32:55 -08:00
• 9f69a70d74 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-12-23 05:10:37 -08:00
• 33a22f8768 Simplified log_spacer() code Clifford Wolf 2016-12-23 02:06:46 +01:00
• a0dff87a57 Added "yosys -W regex" Clifford Wolf 2016-12-22 23:41:44 +01:00
• f144adec58 Added AIGER back-end to automatic back-end detection Clifford Wolf 2016-12-21 10:16:47 +01:00
• f31e6a7174 Updated ABC to hg rev a4872e22c646 Clifford Wolf 2016-12-21 10:16:10 +01:00
• 3d0e51f813 Updated ABC to hg rev 8bab2eedbba4 Clifford Wolf 2016-12-21 09:13:20 +01:00
• ada98844b9 greenpak4: Added INT pin to GP_SPI Andrew Zonenberg 2016-12-21 11:35:29 +08:00
• 6b526e9382 greenpak4: removed unused MISO pin from GP_SPI Andrew Zonenberg 2016-12-21 11:33:32 +08:00
• 638f3e3b12 greenpak4: Removed SPI_BUFFER parameter Andrew Zonenberg 2016-12-20 13:07:49 +08:00
• 073e8df9f1 greenpak4: replaced MOSI/MISO with single one-way SDAT pin Andrew Zonenberg 2016-12-20 12:34:56 +08:00
• d4a05b499e greenpak4: Changed port names on GP_SPI for clarity Andrew Zonenberg 2016-12-20 10:30:38 +08:00
• eb80ec84aa greenpak4: Initial implementation of GP_SPI cell Andrew Zonenberg 2016-12-20 09:58:02 +08:00
• fcd40fd41e Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-12-17 12:02:46 +08:00
• de1d81511a greenpak4: Updated GP_DCMP cell model Andrew Zonenberg 2016-12-17 12:01:22 +08:00
• 7cdba8432c greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF. Andrew Zonenberg 2016-12-16 15:14:20 +08:00
• 3886669ab6 Added "verilog_defines" command Clifford Wolf 2016-12-15 17:49:11 +01:00
• bea6e2f11f greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX Andrew Zonenberg 2016-12-15 15:19:35 +08:00
• 3690aa556c greenpak4: More fixups of GP_DCMPx cells Andrew Zonenberg 2016-12-15 07:19:08 +08:00
• 3491d33863 greenpak4: And another typo :( Andrew Zonenberg 2016-12-15 07:17:07 +08:00
• ea787e6be3 greenpak4: Fixed another typo Andrew Zonenberg 2016-12-15 07:16:26 +08:00
• 58da621ac3 greenpak4: Fixed typo Andrew Zonenberg 2016-12-15 07:15:38 +08:00
• 262f8f913c greenpak4: Cleaned up trailing spaces in cells_sim Andrew Zonenberg 2016-12-14 14:14:45 +08:00
• c77e6e6114 greenpak4: Added GP_DCMPREF / GP_DCMPMUX Andrew Zonenberg 2016-12-14 14:14:26 +08:00
• 00761de1b7 Bugfix in comment handling Clifford Wolf 2016-12-13 13:48:09 +01:00
• 01d8278e53 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-12-12 17:05:06 +08:00
• a61c88f122 Added $anyconst support to AIGER back-end Clifford Wolf 2016-12-11 13:48:18 +01:00
• 8a717ae1dc Merge branch 'LSS-USP-unit-test-structure' Clifford Wolf 2016-12-11 11:03:25 +01:00
• 71c47f13ed Some minor CodingReadme changes in unit test section Clifford Wolf 2016-12-11 11:02:56 +01:00
• 5c96982522 Build hotfix in tests/unit/Makefile Clifford Wolf 2016-12-11 10:58:49 +01:00
• c3c2983d12 Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF Andrew Zonenberg 2016-12-11 10:04:00 +08:00
• b932e2355d Improved unit test structure rodrigosiqueira 2016-12-10 18:21:56 -02:00
• 8f3d1f8fcf greenpak4: Added support for inferred input/output inverters on latches Andrew Zonenberg 2016-12-10 19:58:32 +08:00
• c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) Andrew Zonenberg 2016-12-10 18:46:36 +08:00
• 797c03997e greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency Andrew Zonenberg 2016-12-10 13:57:37 +08:00
• 8767cdcac9 Added GP_DLATCH and GP_DLATCHI Andrew Zonenberg 2016-12-05 23:49:06 -08:00
• 981f014301 Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet. Andrew Zonenberg 2016-12-05 21:22:41 -08:00
• e6ab00d419 Updated help text for synth_greenpak4 Andrew Zonenberg 2016-12-05 20:10:03 -08:00
• 3f2f64f414 Added explanation about configure and create test rodrigosiqueira 2016-12-04 11:35:13 -02:00
• e0152319f5 Added required structure to implement unit tests rodrigosiqueira 2016-12-04 11:28:25 -02:00
• a44cc7a3d1 Added $assert/$assume support to AIGER back-end Clifford Wolf 2016-12-03 13:20:29 +01:00
• 37760541bd Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig Clifford Wolf 2016-12-03 12:37:20 +01:00
• 8a90e61c1a Updated ABV to hg rev 8b555d9e67cf Clifford Wolf 2016-12-01 17:45:40 +01:00
• 105b6374ae Added examples/aiger/ Clifford Wolf 2016-12-01 13:42:17 +01:00
• 88b9733253 Added "yosys-smtbmc --aig" Clifford Wolf 2016-12-01 12:57:26 +01:00
• 52c243cf05 Added support for partially initialized regs to smt2 back-end Clifford Wolf 2016-12-01 12:00:00 +01:00
• 5fa1fa1e6f Added "write_aiger -zinit -symbols -vmap" Clifford Wolf 2016-12-01 11:04:36 +01:00
• c1f762ca56 Added "write_aiger" command Clifford Wolf 2016-11-30 21:30:24 +01:00
• b1cdf772eb Added "design -reset-vlog" Clifford Wolf 2016-11-30 11:25:55 +01:00
• ac7a175a3c Improved equiv_purge log output Clifford Wolf 2016-11-29 13:30:35 +01:00
• df2e5aad6f Bugfix in smt2 back-end for pure checker modules Clifford Wolf 2016-11-28 15:15:09 +01:00
• ecdc22b06c Added support for macros as include file names Clifford Wolf 2016-11-28 14:50:17 +01:00
• c7f6fb6e17 Bugfix in "read_verilog -D NAME=VAL" handling Clifford Wolf 2016-11-28 14:45:05 +01:00
• c17d98f55c Removed shebang line from smtio.py, fixes #279 Clifford Wolf 2016-11-27 12:11:04 +01:00