1
0
mirror of synced 2026-05-22 21:40:08 +00:00

Commit Graph

  • 847558547b functional.cc: Reverse port iteration Krystine Sherwin 2025-05-21 16:21:27 +12:00
  • 3001473ae5 functional.cc: Maintain port ordering Krystine Sherwin 2025-05-21 16:09:39 +12:00
  • 8ec9de00ec Use ir.inputs()/ir.outputs() Gus Smith 2025-05-20 17:45:23 -07:00
  • af51097af7 Convert to 'assoc list helpers' Gus Smith 2025-05-18 18:01:43 -07:00
  • a55dc80175 Rename parameter Gus Smith 2025-05-17 16:04:17 -07:00
  • c1111f125c Add output helper as well Gus Smith 2025-05-17 15:19:09 -07:00
  • 1fdfba2a1a Add helper for accessing by base name Gus Smith 2025-05-17 15:17:29 -07:00
  • 10b8fdddb4 Rename argument Gus Smith 2025-05-17 14:39:11 -07:00
  • 7b4c9c5dcd Add optional keyword-based constructor Gus Smith 2025-05-17 14:12:09 -07:00
  • fd5918c811 get_field_names for structs Gus Smith 2025-05-17 14:10:23 -07:00
  • 64a115e6f0 Disable STRIP operations when appropriate. RonxBulld 2025-05-18 01:07:06 +08:00
  • 388955031f Bump version github-actions[bot] 2025-05-17 00:23:43 +00:00
  • 135320a58c Merge pull request #5123 from cr1901/winstat-fix KrystalDelusion 2025-05-17 09:33:18 +12:00
  • 7d4d544001 Strip trailing slashes when checking for directories on Windows. William D. Jones 2025-05-15 18:36:04 -04:00
  • 4c72b0ecd8 Merge pull request #5116 from YosysHQ/krys/update_fst KrystalDelusion 2025-05-16 09:22:52 +12:00
  • 3a5ce2df64 Merge pull request #5112 from YosysHQ/krys/on_shutdown KrystalDelusion 2025-05-16 09:22:39 +12:00
  • f7888c607b Merge pull request #5089 from YosysHQ/krys/cutpoint_whole KrystalDelusion 2025-05-16 09:22:28 +12:00
  • 3823157c25 Merge pull request #5080 from akashlevy/muldiv_c Emil J 2025-05-15 11:03:25 +02:00
  • ae47c49af5 Bump version github-actions[bot] 2025-05-15 00:22:59 +00:00
  • 748600c167 small whitespace cleanup (#5119) George Rennie 2025-05-14 14:18:57 +01:00
  • 45452c18b2 write_verilog: write module ports in order backends/verilog/verilog_backend.cc Emil J. Tywoniak 2025-05-14 14:34:50 +02:00
  • e3ae7b1400 Bump version github-actions[bot] 2025-05-13 00:24:04 +00:00
  • 5268565410 Merge pull request #5108 from marzoul/adrien-uram KrystalDelusion 2025-05-13 09:54:36 +12:00
  • c590c0c12c Merge pull request #5111 from YosysHQ/krys/config_python KrystalDelusion 2025-05-13 09:54:26 +12:00
  • 05157b164e Merge pull request #5113 from YosysHQ/krys/ast_asan KrystalDelusion 2025-05-13 09:52:51 +12:00
  • f73c6a9c9a write_verilog: don't dump single_bit_vector attribute Emil J. Tywoniak 2025-05-12 13:36:25 +02:00
  • e5171d6aa1 verific: support single_bit_vector Emil J. Tywoniak 2025-05-12 13:23:02 +02:00
  • 5e72464a15 rtlil: enable single-bit vector wires Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
  • afd5bbc7fa fstdata.cc: Fix last step Krystine Sherwin 2025-05-12 13:18:19 +12:00
  • d0b9a0cb98 sim.cc: Move cycle check Krystine Sherwin 2025-05-12 12:48:01 +12:00
  • cc402ee065 libs/fst: Update upstream Krystine Sherwin 2025-05-12 10:21:06 +12:00
  • 586fa033a6 design: ensure all_modules outlives pass when building WITH_PYTHON emil/fix-design-lifetime-with-pyosys Emil Jiří Tywoniak 2025-05-10 17:19:51 +02:00
  • 6bf7587338 URAM mapping : Add test for 2048 x 144b Adrien Prost-Boucle 2025-05-10 14:53:56 +02:00
  • fe0abb7026 simplify.cc: Fix mem leak Krystine Sherwin 2025-05-10 17:10:47 +12:00
  • 6900818105 Bump version github-actions[bot] 2025-05-10 00:22:55 +00:00
  • af75dce660 Fix Crashes with GCC 15 #5088 Krystine Sherwin 2025-05-10 09:59:13 +12:00
  • c4af97c1c4 Merge pull request #5110 from YosysHQ/emil/gzip-reject-directory KrystalDelusion 2025-05-10 09:36:13 +12:00
  • 1e2d6508d0 Makefile: Conditional assignment of python exe KrystalDelusion 2025-05-10 09:09:30 +12:00
  • 2e9a194ce9 gzip: reject uncompressing directories Emil J. Tywoniak 2025-05-09 21:23:34 +02:00
  • b05c0c70af io: don't accept a directory when file expected Emil J. Tywoniak 2025-05-09 22:30:43 +02:00
  • cbf069849e aiger: add regression test for sliced output segfault Emil Jiří Tywoniak 2025-05-09 16:01:47 +02:00
  • c7de531231 URAM mapping : Fix port indexes according to Yosys warnings Adrien Prost-Boucle 2025-05-09 15:09:11 +02:00
  • 2522bcd492 aiger: fix -map and -vmap Emil J. Tywoniak 2025-05-09 14:21:10 +02:00
  • c4a49f0c55 Create a single-port URAM mapping to support memories 2048 x 144b Adrien Prost-Boucle 2025-05-09 14:16:03 +02:00
  • 2ca2ecaa1c libcache: fix help Emil J. Tywoniak 2025-05-09 12:40:45 +02:00
  • 9d2f9f7557 libcache: fix test Emil J. Tywoniak 2025-05-09 12:40:38 +02:00
  • 0d621ecc11 libcache: add -quiet and -verbose Emil J. Tywoniak 2025-05-09 11:36:39 +02:00
  • 55bd950af4 Bump version github-actions[bot] 2025-05-09 00:27:47 +00:00
  • 5aa9bfbf7d Merge pull request #5098 from mikesinouye/hashlib-1 Emil J 2025-05-08 19:05:10 +02:00
  • bfbbb8cf98 Merge pull request #5086 from YosysHQ/emil/driver-no-version Emil J 2025-05-08 16:28:25 +02:00
  • 068dd77a14 check: fix up tests emil/check-harder Emil J. Tywoniak 2025-05-08 12:37:10 +02:00
  • d3894caf25 logger: allow multiple regexes for -expect error Emil J. Tywoniak 2025-05-08 12:35:25 +02:00
  • 051c00e7db use scratchpad variable check.permissive Emil J. Tywoniak 2025-05-07 17:52:31 +02:00
  • 56d562299a remove invalid tests, use scratchpad variable check.permissive Emil J. Tywoniak 2025-05-07 15:26:09 +02:00
  • 0601260bf2 check: add scratchpad check.permissive and use it Emil J. Tywoniak 2025-05-08 14:37:03 +02:00
  • d59380b3a0 tests: more complete testing of shift edgecases George Rennie 2025-05-08 11:09:01 +02:00
  • e2485000c7 kernel: handle unsigned case for as_int_saturating correctly George Rennie 2025-05-08 11:08:20 +02:00
  • 547382504b Update verilog_frontend.cc KrystalDelusion 2025-05-08 10:37:04 +12:00
  • 68c11321c0 remove invalid tests emil/check-harder-fix-tests Emil J. Tywoniak 2025-05-07 17:52:31 +02:00
  • 420d65dd9d remove invalid tests Emil J. Tywoniak 2025-05-07 15:26:09 +02:00
  • af933b4f38 tests: check shifts by amounts that overflow int George Rennie 2025-05-07 15:12:33 +02:00
  • 0dcd94b6ad opt_expr: saturate shift amount instead of overflowing for large shifts George Rennie 2025-05-07 14:41:13 +02:00
  • 7cbe6ed048 kernel: add safer variants of as_int George Rennie 2025-05-07 14:36:48 +02:00
  • 6378ba10eb Merge pull request #5078 from RonxBulld/main Emil J 2025-05-07 11:34:46 +02:00
  • 90a2c92370 driver: allow --no-version still write things like Generated by Yosys Emil J. Tywoniak 2025-05-07 11:34:23 +02:00
  • 8da97d0044 Bump version github-actions[bot] 2025-05-07 00:24:00 +00:00
  • 93780bb869 Add <optional> to haslib.h which uses std::optional mikesinouye 2025-05-06 09:57:03 -07:00
  • a0e94e506d Merge pull request #5094 from pu-cc/gatemate-reduce-bram-cpes Miodrag Milanović 2025-05-06 15:19:56 +02:00
  • 20921ad908 Next dev cycle Miodrag Milanovic 2025-05-06 08:26:46 +02:00
  • 53c22ab7c0 Release version 0.53 v0.53 Miodrag Milanovic 2025-05-06 07:45:16 +02:00
  • 5924f2de7b Bump version github-actions[bot] 2025-05-06 00:23:55 +00:00
  • 7c89355b70 cutpoint: Re-add whole module optimization Krystine Sherwin 2025-05-06 09:57:34 +12:00
  • d7affb8821 driver: add --no-version to suppress writing Yosys version in command outputs Emil J. Tywoniak 2025-05-05 13:12:08 +02:00
  • f60bbe64ac Merge pull request #5085 from YosysHQ/krys/fix_5069 Emil J 2025-05-05 10:39:43 +02:00
  • 7c2b00c448 tests: Add default param test file Krystine Sherwin 2025-05-05 10:18:52 +12:00
  • 23cb007068 verilog_parser.y: Delete unused TOK_ID Krystine Sherwin 2025-05-05 10:04:13 +12:00
  • 765485a375 Bump version github-actions[bot] 2025-05-04 00:26:28 +00:00
  • da1ac9ae47 cxxrtl: fix missing sign extension before shift operation for signed values sdjasj 2025-05-03 17:38:16 +08:00
  • aa30589c12 Bump version github-actions[bot] 2025-05-01 00:26:28 +00:00
  • 4213f75caa Merge pull request #4969 from YosysHQ/krys/check_yosys_git KrystalDelusion 2025-05-01 10:09:08 +12:00
  • 22c72a5af4 Merge pull request #4619 from malmeloo/fix/tee-path-whitespace KrystalDelusion 2025-05-01 09:33:47 +12:00
  • 11c846de5c aiger, xaiger, aiger2: add -no_version emil/aiger-no_version Emil J. Tywoniak 2025-04-30 19:36:14 +02:00
  • 11f2348246 Merge pull request #5073 from YosysHQ/emil/fix-uncompressed-missing-file-error Emil J 2025-04-30 19:29:13 +02:00
  • 4bd91fbb11 Add muldiv_c peepopt pass Akash Levy 2025-04-30 08:06:59 -07:00
  • 15cfce061a Change the implementation of log_debug in kernel/log.h from a macro function to a normal function. RonxBulld 2025-04-29 22:43:10 +08:00
  • adb1986dc1 gzip: refactor file open failure errors Emil J. Tywoniak 2025-04-29 10:37:35 +02:00
  • bfe05965f9 Merge pull request #5066 from YosysHQ/george/opt_expr_shr_sign KrystalDelusion 2025-04-29 09:29:10 +12:00
  • ff2a8af545 quicklogic: workaround for #5069 emil/quicklogic-sv-empty-param-workaround Emil J. Tywoniak 2025-04-28 16:01:12 +02:00
  • 8bdbf797d0 Merge pull request #5017 from YosysHQ/micko/ram_blasting N. Engelhardt 2025-04-28 13:33:48 +00:00
  • 84c49e1f33 Merge pull request #5041 from jix/declockgate-v2 N. Engelhardt 2025-04-28 13:31:11 +00:00
  • 6d575918fc gatemate: Set unused BRAM inputs to 'bx Patrick Urban 2025-04-28 14:42:16 +02:00
  • f0545d5bc1 simplify: fix another struct wiretype attr memory leak emil/fix-dangling-wiretype-2 Emil J. Tywoniak 2025-04-28 13:18:00 +02:00
  • ab614b1271 Merge pull request #5061 from YosysHQ/emil/fix-driver-xtrace Emil J 2025-04-28 10:31:40 +02:00
  • 58e7cfa559 Bump version github-actions[bot] 2025-04-27 00:25:27 +00:00
  • 4fbb2bc1f3 celledges: use capped shift width George Rennie 2025-04-26 18:34:21 +02:00
  • 3d1f2161dc cxxrtl: strip $paramod from module name in scope info. Catherine 2024-11-14 21:49:53 +00:00
  • 70a44f035c tests: test opt_expr constant shift edge cases George Rennie 2025-04-26 12:10:53 +02:00
  • c952ab417f opt_expr: only sign extend shift arguments for arithmetic right shift George Rennie 2025-04-26 12:03:50 +02:00
  • 2d6255175e Merge pull request #5057 from secworks/blocking_assignment_greenpak4_cells_sim_digital KrystalDelusion 2025-04-26 11:15:10 +12:00
  • 6564810ae3 Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned KrystalDelusion 2025-04-26 11:15:02 +12:00