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Mono Color

• afcc31ceba Bump version Yosys Bot 2021-02-04 00:10:05 +00:00
• 4bc6995b9a Merge pull request #2436 from dalance/fix_generate whitequark 2021-02-03 09:43:23 +00:00
• 5eff0b73ae Provide an integer implementation of decimal_digits(). Henner Zeller 2021-02-01 11:23:44 -08:00
• fe74b0cd95 verilog: significant block scoping improvements Zachary Snow 2021-01-27 13:30:22 -05:00
• beeaad1904 Bump version Yosys Bot 2021-01-31 00:10:05 +00:00
• d99c032c27 Require latest Verific build Miodrag Milanovic 2021-01-30 09:23:46 +01:00
• 1057273852 Bump version Yosys Bot 2021-01-30 00:10:05 +00:00
• a4c04d1b90 ast: fix dump_vlog display of casex/casez Marcelina Kościelnicka 2021-01-28 00:31:50 +01:00
• 708eb327a1 Merge pull request #2564 from whitequark/flatten-improve-error whitequark 2021-01-29 02:55:51 +00:00
• ffa1cb836b Bump version Yosys Bot 2021-01-29 00:10:05 +00:00
• 74b0c38520 Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces whitequark 2021-01-28 21:32:27 +00:00
• d0d7a360ed Merge pull request #2535 from Ravenslofty/scc-specify Claire Xen 2021-01-28 19:01:29 +01:00
• 27257a419f verilog: strip leading and trailing spaces in macro args Zachary Snow 2021-01-28 11:26:21 -05:00
• 98afe2b758 Bump version Yosys Bot 2021-01-27 00:10:04 +00:00
• ea79e16bab xilinx_dffopt: Don't crash on missing IS_*_INVERTED. Marcelina Kościelnicka 2021-01-25 13:01:18 +01:00
• cd6f0732f3 xilinx: Add FDRSE_1, FDCPE_1. Marcelina Kościelnicka 2021-01-25 13:01:24 +01:00
• a77fa6709b Merge pull request #2563 from whitequark/cxxrtl-msvc whitequark 2021-01-26 21:55:12 +00:00
• d73ffa07f2 Merge pull request #2544 from modwizcode/fix-clock whitequark 2021-01-26 21:18:06 +00:00
• 2364820f50 flatten: clarify confusing error message. whitequark 2021-01-26 18:29:16 +00:00
• 4b6e764c46 cxxrtl: do not use ->template for non-dependent names. whitequark 2021-01-26 17:42:23 +00:00
• 74dad5afe7 scc: Add -specify option to find loops in boxes Dan Ravensloft 2021-01-11 18:37:27 +00:00
• 8eaeaa8434 Bump version Yosys Bot 2021-01-26 00:10:05 +00:00
• f200a8fe1c Merge pull request #2549 from pgadfort/support-multiple-libs whitequark 2021-01-25 10:36:14 +00:00
• ffbd813a8c Merge pull request #2550 from zachjs/macro-arg-spaces whitequark 2021-01-25 10:36:07 +00:00
• 410ea42242 Bump version Yosys Bot 2021-01-25 00:10:07 +00:00
• 2257a9a721 Merge pull request #2558 from YosysHQ/dave/chandle-dpi Claire Xen 2021-01-24 02:45:08 +01:00
• 09311b6581 dpi: Support for chandle type David Shah 2021-01-23 22:24:31 +00:00
• 54294957ed Bump version Yosys Bot 2021-01-22 00:10:05 +00:00
• 7d014902ec Fix digit-formatting calculation for small numbers. Henner Zeller 2021-01-21 12:20:53 -08:00
• 1f88a3de74 Merge pull request #2553 from zachjs/rand-const-modifiers Miodrag Milanović 2021-01-21 16:56:19 +01:00
• 1096b969ef Allow combination of rand and const modifiers Zachary Snow 2021-01-21 08:30:55 -07:00
• 699a98b265 Bump version Yosys Bot 2021-01-21 00:10:05 +00:00
• b734f2c932 Merge pull request #2552 from YosysHQ/claire/yosyshq Claire Xen 2021-01-21 00:54:45 +01:00
• acad7a6e40 Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific Claire Xenia Wolf 2021-01-20 20:48:10 +01:00
• bfa353f154 Merge pull request #2536 from TobiasFaller/master Miodrag Milanović 2021-01-20 20:42:02 +01:00
• 00f02e0589 Merge pull request #2551 from zachjs/wire-logic Miodrag Milanović 2021-01-20 18:31:49 +01:00
• 006c18fc11 sv: fix support wire and var data type modifiers Zachary Snow 2021-01-20 09:15:48 -07:00
• 4fadcc8f25 verilog: allow spaces in macro arguments Zachary Snow 2021-01-20 08:49:32 -07:00
• 169234d6e9 adding support for passing multiple liberty files to abc Peter Gadfort 2021-01-18 16:47:49 -05:00
• 4762cc06c6 Bump version Yosys Bot 2021-01-19 00:10:05 +00:00
• e991ceeef3 Merge pull request #2547 from zachjs/plugin-so-dsym whitequark 2021-01-18 20:21:20 +00:00
• 056c12eb6f Merge pull request #2312 from antmicro/typedef-inout whitequark 2021-01-18 20:20:52 +00:00
• 4c108b4419 Add plugin.so.dSYM to .gitignore Zachary Snow 2021-01-18 11:13:21 -07:00
• d69ddf19da Add typedef input/output test Kamil Rakoczy 2020-07-08 13:44:03 +02:00
• 61501e3266 Fix input/output attributes when resolving typedef of wire Kamil Rakoczy 2020-06-09 09:53:00 +02:00
• 09071afe15 Parse package user type in module port list Lukasz Dalek 2020-05-19 17:13:04 +02:00
• c8415884d1 Improves the previous commit with a more complete coverage of the cases Iris Johnson 2021-01-15 13:59:20 -06:00
• 339848b954 Bump version Yosys Bot 2021-01-15 00:10:05 +00:00
• 86607d0fdc Handle sliced bits as clock inputs (fixes #2542) Iris Johnson 2021-01-14 16:26:20 -06:00
• 01626e6746 opt_share: Fix X and CO signal width for shifted $alu in opt_share. Marcelina Kościelnicka 2021-01-14 09:58:33 +01:00
• 7cd044bbc4 Bump version Yosys Bot 2021-01-14 00:10:05 +00:00
• 0927675147 Merge pull request #2537 from pepijndevos/spice Claire Xen 2021-01-13 19:08:25 +01:00
• e789a00557 add buffer option to spice backend Pepijn de Vos 2021-01-13 17:24:28 +01:00
• 760a2c1343 Fixed missing goto statement in passes/techmap/abc.cc Tobias Faller 2021-01-12 16:17:51 +01:00
• b0004911ca Bump version Yosys Bot 2021-01-05 00:10:05 +00:00
• b00e55a16a Merge pull request #2522 from tomverbeure/simlib_typos2 whitequark 2021-01-04 14:04:17 +00:00
• c4e23aab55 Add boost-python3 Xiangyu Xu 2021-01-04 03:23:09 -06:00
• 3a8eecebba Fix indents. Tom Verbeure 2021-01-04 00:17:16 -08:00
• bb3439562e Add -nosynthesis flag for read_verilog command. Tom Verbeure 2021-01-04 00:11:01 -08:00
• 87637e8359 Fix some trivial typos. Tom Verbeure 2021-01-03 23:52:59 -08:00
• b72c294653 Bump version Yosys Bot 2021-01-02 00:10:04 +00:00
• b0d4c63957 Merge pull request #2480 from YosysHQ/dave/nexus-lram whitequark 2021-01-01 09:49:00 +00:00
• 1387c3b41d Merge pull request #2512 from umarcor/plugin-err whitequark 2021-01-01 09:39:17 +00:00
• 8759ed9883 Merge pull request #2515 from umarcor/fix/ghdl whitequark 2021-01-01 09:37:12 +00:00
• bc2de4567c Merge pull request #2518 from zachjs/recursion whitequark 2021-01-01 09:32:26 +00:00
• 1a80194cd3 Merge pull request #2517 from zachjs/sv-tf-implied-direction whitequark 2021-01-01 09:31:49 +00:00
• 2085d9a55d verilog: improved support for recursive functions Zachary Snow 2020-12-31 17:23:36 -07:00
• 75abd90829 sv: complete support for implied task/function port directions Zachary Snow 2020-12-31 16:14:35 -07:00
• 7f28afd3ac makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX umarcor 2020-12-30 07:06:52 +01:00
• 48d0aeb094 Bump version Yosys Bot 2020-12-30 00:10:06 +00:00
• e61b107072 plugin: enhance no-plugin error umarcor 2020-12-28 04:30:57 +01:00
• da1d06d785 Merge pull request #2509 from zachjs/issue-2427 whitequark 2020-12-29 02:59:09 +00:00
• e609bc4898 Merge pull request #2514 from umarcor/feat/ghdl whitequark 2020-12-29 02:58:41 +00:00
• 0347b441a1 Bump version Yosys Bot 2020-12-29 00:10:04 +00:00
• a652430c71 makefile: add support for built-in ghdl-yosys-plugin umarcor 2020-12-28 02:24:41 +01:00
• c718780ff6 Merge pull request #2511 from umarcor/feat/msys2-32 whitequark 2020-12-28 02:33:58 +00:00
• f4a800899c Merge pull request #2507 from umarcor/fix/msys2 whitequark 2020-12-28 02:33:30 +00:00
• 0ebce301c1 makefile: rename msys2 to msys2-32, config PREFIX umarcor 2020-12-27 05:37:46 +01:00
• 16c4182c74 kernel/yosys.h: undef CONST on WIN32 umarcor 2020-12-26 23:21:30 +01:00
• f48298347c Bump version Yosys Bot 2020-12-28 00:10:04 +00:00
• d30063ea65 Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast Claire Xen 2020-12-27 16:33:58 +01:00
• cb2283389d CODEOWNERS: add @zachjs as Verilog/AST frontend owner whitequark 2020-12-27 05:00:04 +00:00
• 750831e3e0 Fix elaboration of whole memory words used as indices Zachary Snow 2020-12-26 21:38:13 -07:00
• af457ce8d0 Bump version Yosys Bot 2020-12-27 00:10:10 +00:00
• ce7f06f76e Merge pull request #2506 from zachjs/const-arg-redeclare Miodrag Milanović 2020-12-26 18:59:06 +01:00
• 1419c8761c Fix constants bound to redeclared function args Zachary Snow 2020-12-26 08:39:57 -07:00
• 4491548037 Bump version Yosys Bot 2020-12-24 00:10:08 +00:00
• 54466dc653 Merge pull request #2502 from ldoolitt/master whitequark 2020-12-23 23:36:13 +00:00
• deff6a9546 Merge pull request #2501 from zachjs/genrtlil-tern-sign whitequark 2020-12-23 23:15:56 +00:00
• 8ef6b77dc3 Merge pull request #2476 from zachjs/const-arg-width whitequark 2020-12-23 23:15:30 +00:00
• 84c0b5c690 passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings Larry Doolittle 2020-12-23 14:38:25 -08:00
• 999eec5617 genrtlil: fix mux2rtlil generated wire signedness Zachary Snow 2020-12-22 17:38:51 -07:00
• 832f6aa777 Bump version Yosys Bot 2020-12-23 00:10:07 +00:00
• 8206546c45 Fix constants bound to single bit arguments (fixes #2383) Zachary Snow 2020-12-05 18:56:18 -07:00
• d15c63effc Merge pull request #2499 from whitequark/cxxrtl-fixes whitequark 2020-12-22 12:00:38 +00:00
• f14074d2c2 cxxrtl: don't crash generating debug information for unused wires. whitequark 2020-12-22 06:46:44 +00:00
• 2b62b5ef34 Merge pull request #2498 from StefanBruens/Fix_opt_lut whitequark 2020-12-22 06:15:04 +00:00
• 4949ef1247 Merge pull request #2497 from whitequark/cxxrtl-reflow whitequark 2020-12-22 06:12:39 +00:00
• 7378194169 cxxrtl: split processes into sync and case nodes. whitequark 2020-12-22 00:07:45 +00:00
• ac988cfac5 kernel: undef Tcl macros interfering with cxxrtl. whitequark 2020-12-21 21:17:33 +00:00