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Mono Color

• b117f9bba8 Merge pull request #2633 from whitequark/cxxrtl-no-top whitequark 2021-03-05 04:14:07 -08:00
• 14ce8bdaa6 cxxrtl: follow aliases to outlines when emitting $memrd.ADDR. whitequark 2021-03-05 12:08:48 +00:00
• 8471808834 cxxrtl: add pass debug flag to show assigned wire types. whitequark 2021-03-05 11:44:39 +00:00
• a9a873a1d2 cxxrtl: don't crash on empty designs. whitequark 2021-03-05 11:05:19 +00:00
• c18ddbcd82 verilog: impose limit on maximum expression width Zachary Snow 2021-03-04 15:08:16 -05:00
• 7d2097b005 Update command-reference-manual.tex Claire Xen 2021-03-04 16:45:21 +01:00
• 6c56c083f8 Update README Claire Xen 2021-03-04 16:43:30 +01:00
• 90b40aa51f clk2fflogic: nice names for autogenerated signals Noah Moroze 2021-03-02 18:28:56 -05:00
• d738b2c127 sv: support for parameters without default values Zachary Snow 2021-03-02 10:43:53 -05:00
• 375af199ef Merge pull request #2620 from zachjs/port-int-types whitequark 2021-03-01 22:46:07 -08:00
• 10a6bc9b81 verilog: fix sizing of ports with int types in module headers Zachary Snow 2021-03-01 13:31:25 -05:00
• 0e0f84299a Bump version Marcelina Kościelnicka 2021-03-01 19:33:05 +01:00
• 1ec5994100 verilog: fix handling of nested ifdef directives Zachary Snow 2021-02-25 15:53:55 -05:00
• b6904a8e53 Set aside extraneous tests in simple_abc9 test suite Zachary Snow 2021-02-09 19:58:15 -05:00
• 004b780b8a Merge pull request #2523 from tomverbeure/define_synthesis Claire Xen 2021-03-01 18:00:48 +01:00
• 527c681a2b Merge pull request #2524 from bkbncn/patch-1 Claire Xen 2021-03-01 17:46:33 +01:00
• 7b47dd0f88 Merge pull request #2617 from RobertBaruch/doc whitequark 2021-03-01 08:10:32 -08:00
• ca5f5ffcd6 Merge pull request #2615 from zachjs/genrtlil-conflict whitequark 2021-03-01 08:10:19 -08:00
• 0fb4224ebc Merge pull request #2618 from zachjs/int-types whitequark 2021-02-28 20:29:44 -08:00
• 0f5b646ab8 sv: extended support for integer types Zachary Snow 2021-02-28 15:49:16 -05:00
• ca4b1afcb6 RTLIL Documentation: switch in process is optional Robert Baruch 2021-02-27 09:58:03 -08:00
• d882b6fe3c Update issue_template.md Claire Xen 2021-02-27 16:52:30 +01:00
• bbff844acd genrtlil: improve name conflict error messaging Zachary Snow 2021-02-26 18:08:23 -05:00
• d56b76bd7c Add tests for $countbits Michael Singer 2021-02-25 01:21:36 +01:00
• 04b41ed04a Implement $countones, $isunknown and $onehot{,0} Michael Singer 2021-02-23 01:19:06 +01:00
• 8434ba5a3b Implement $countbits function Michael Singer 2021-02-23 00:55:55 +01:00
• 22bed38540 Extend simplify() recursion warning Zachary Snow 2021-02-25 16:02:55 -05:00
• 5d0cc54f5c Bump version Marcelina Kościelnicka 2021-02-26 00:24:33 +01:00
• 58a5755187 Merge pull request #2554 from hzeller/master whitequark 2021-02-25 13:54:16 -08:00
• 979347999f btor, smt2, smv: Add a hint on how to deal with funny FF types. Marcelina Kościelnicka 2021-02-23 12:06:21 +01:00
• a651204efa Fix handling of unique/unique0/priority cases in the frontend. Marcelina Kościelnicka 2021-02-22 19:19:42 +01:00
• dcd9f0af23 Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) TimRudy 2021-02-24 15:48:15 -05:00
• fffbf651df Merge pull request #2607 from zachjs/logger-error-atexit whitequark 2021-02-24 19:12:56 +00:00
• 5e439b6e3f Fix double-free on unmatched logger error pattern Zachary Snow 2021-02-23 20:39:13 -05:00
• b05b98521c Add tests for some common techmap files. Marcelina Kościelnicka 2021-02-23 21:23:26 +01:00
• cde73428b0 Fix syntax error in adff2dff.v Marcelina Kościelnicka 2021-02-23 12:12:37 +01:00
• f4f471f342 frontend: Make helper functions for printing locations. Marcelina Kościelnicka 2021-02-23 19:22:53 +01:00
• ad2960adb7 Merge pull request #2594 from zachjs/func-arg-width whitequark 2021-02-23 21:46:16 +00:00
• 4b31223e60 int -> bool Robert Baruch 2021-02-21 20:00:31 -08:00
• 7c50b89b24 Adds is_wire to SigBit and SigChunk Robert Baruch 2021-02-20 11:46:30 -08:00
• ae07298a6b machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. William D. Jones 2021-02-21 09:14:37 -05:00
• 353ace5034 machxo2: Update tribuf test to reflect active-low OE. William D. Jones 2021-02-10 18:50:17 -05:00
• 8f1a350f5e machxo2: Add experimental status to help. William D. Jones 2021-02-08 17:31:58 -05:00
• e3974809ec machxo2: Add DCCA and DCMA blackbox primitives. William D. Jones 2021-01-31 23:57:13 -05:00
• a1ea1430b6 machxo2: Fix reversed interpretation of REG_SD config bits. William D. Jones 2021-01-31 19:05:15 -05:00
• 4e9def23de machxo2: Tristate is active-low. William D. Jones 2021-01-31 11:33:20 -05:00
• 8b14152506 machxo2: Fix typos in FACADE_FF sim model. William D. Jones 2021-01-30 23:55:00 -05:00
• 8348c45e4f machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. William D. Jones 2021-01-29 18:14:13 -05:00
• 120404bfda machxo2: Improve help_mode output in synth_machxo2. William D. Jones 2020-12-13 00:34:01 -05:00
• 3674eb34d4 machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells. William D. Jones 2020-12-12 18:09:52 -05:00
• 124780ecd9 machxo2: Add missing OSCH oscillator primitive. William D. Jones 2020-12-07 22:29:36 -05:00
• c31b17a2e2 machxo2: Add believed-to-be-correct tribuf test. William D. Jones 2020-11-26 22:34:46 -05:00
• c7aaa88f58 machxo2: Add passing fsm, mux, and shifter tests. William D. Jones 2020-11-26 22:30:48 -05:00
• 453904dd00 machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. William D. Jones 2020-11-26 21:58:20 -05:00
• 597a54dbd0 machxo2: Add -noiopad option to synth_machxo2. William D. Jones 2020-11-26 21:23:13 -05:00
• 3697f351d5 machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. William D. Jones 2020-11-26 20:18:15 -05:00
• f07b8eb606 machxo2: Fix cells_sim typo where OFX1 was multiply-driven. William D. Jones 2020-11-26 18:47:11 -05:00
• c76f361b56 machxo2: synth_machxo2 now maps ports to FACADE_IO. William D. Jones 2020-11-26 13:39:40 -05:00
• 03cbf1327d machxo2: Add initial value for Q in FACADE_FF. William D. Jones 2020-11-21 18:44:42 -05:00
• 0364ded385 machxo2: Add FACADE_IO simulation model. More comments on models. William D. Jones 2020-11-21 11:58:30 -05:00
• 1b703d3f03 machxo2: Add FACADE_SLICE simulation model. William D. Jones 2020-11-21 11:53:30 -05:00
• cc52eb53cd machxo2: Improve FACADE_FF simulation model. William D. Jones 2020-11-20 21:24:39 -05:00
• 427fed23ee machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. William D. Jones 2020-11-20 18:53:09 -05:00
• 19b043344c machxo2: Add dffe test. William D. Jones 2020-11-20 18:16:45 -05:00
• 84937e9689 machxo2: Add dff.ys test, fix another cells_map.v typo. William D. Jones 2020-11-17 14:35:17 -05:00
• 044393b990 machxo2: Fix more oversights in machxo2 models. logic.ys test passes. William D. Jones 2020-11-17 14:22:44 -05:00
• 9cb0bae1b2 machxo2: Add test/arch/machxo2 directory (test does not pass). William D. Jones 2020-11-17 13:01:57 -05:00
• b87f6a0906 machxo2: Fix typos. test/arch/run-test.sh passes. William D. Jones 2020-11-17 12:49:15 -05:00
• 88c8f81260 machxo2: Create basic techlibs and synth_machxo2 pass. William D. Jones 2020-11-16 15:07:32 -05:00
• cc7d18d29a frontend: json: parse negative values Karol Gugala 2021-01-27 20:34:00 +01:00
• 4746ffd7b2 assertpmux: Fix crash on unused $pmux output. Marcelina Kościelnicka 2021-02-22 22:02:48 +01:00
• 01ccb80b70 Merge pull request #2586 from zachjs/tern-recurse whitequark 2021-02-21 20:56:04 +00:00
• 3fee43cde0 Merge pull request #2591 from zachjs/verilog-preproc-unapplied whitequark 2021-02-21 20:53:56 +00:00
• b6af90fe20 verilog: fix sizing of constant args for tasks/functions Zachary Snow 2021-02-21 14:45:21 -05:00
• 220cb1f7bb verilog: error on macro invocations with missing argument lists Zachary Snow 2021-02-18 12:04:02 -05:00
• 127484e675 Bump version Yosys Bot 2021-02-18 00:10:06 +00:00
• dbaccfbabe Merge pull request #2590 from RobertBaruch/fix_fast_sop_mode Claire Xen 2021-02-17 16:30:12 +01:00
• 1d79222af4 Fixes command line for abc pass in -fast -sop mode Robert Baruch 2021-02-16 16:34:09 -08:00
• 78684596dc Bump version Yosys Bot 2021-02-16 00:10:06 +00:00
• 27d7741540 Merge pull request #2574 from dh73/master Claire Xen 2021-02-15 17:49:11 +01:00
• 4e741adda9 Bump version Yosys Bot 2021-02-13 00:10:04 +00:00
• 8de2e863af verilog: support recursive functions using ternary expressions Zachary Snow 2021-02-12 14:25:34 -05:00
• 9f7cd10c98 Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct gatecat 2021-02-12 12:07:12 +00:00
• 13c2fd7137 Ganulate Verific support Miodrag Milanovic 2021-02-12 10:08:43 +01:00
• 17c895cbf8 Bump version Yosys Bot 2021-02-12 00:10:05 +00:00
• 326f1c9db4 Merge pull request #2573 from zachjs/repeat-call whitequark 2021-02-11 19:56:41 +00:00
• 73d611990d Merge pull request #2578 from zachjs/genblk-port Zachary Snow 2021-02-11 10:26:49 -05:00
• c383d156e9 Merge pull request #2584 from antmicro/atom_type_signedness Zachary Snow 2021-02-11 10:26:06 -05:00
• 7533534429 Add missing is_signed to type_atom Kamil Rakoczy 2021-02-11 12:53:07 +01:00
• 1d5f3fe506 verlog: allow shadowing module ports within generate blocks Zachary Snow 2021-02-06 23:54:17 -05:00
• eff18a2b15 Bump version Yosys Bot 2021-02-07 00:10:04 +00:00
• 331de7a518 Merge pull request #2576 from zachjs/port-bind-sign-uniop whitequark 2021-02-06 19:25:32 +00:00
• 4b2f977331 genrtlil: fix signed port connection codegen failures Zachary Snow 2021-02-05 19:38:10 -05:00
• 2f64f96129 Bump version Yosys Bot 2021-02-06 00:10:05 +00:00
• 3d9898272a Merge pull request #2572 from antmicro/check-labels whitequark 2021-02-05 06:49:34 +00:00
• 7c6bf42db8 Bump version Yosys Bot 2021-02-05 00:10:05 +00:00
• c96eb2fbd7 Accept disable case for SVA liveness properties. Diego H 2021-02-04 15:35:35 -06:00
• 98c4feb72f Add check of begin/end labels for genblock Kamil Rakoczy 2021-02-04 12:12:59 +01:00
• b93b6f4285 verilog: refactored constant function evaluation Zachary Snow 2021-01-27 13:21:13 -05:00
• baf1875307 Merge pull request #2529 from zachjs/unnamed-genblk whitequark 2021-02-04 09:57:28 +00:00