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Mono Color

• a23d9409e7 opt_mem: Remove write ports with const-0 EN. Marcelina Kościelnicka 2021-05-22 20:27:51 +02:00
• 039f4f48d5 memory_memx: Use Mem helper. Marcelina Kościelnicka 2021-05-22 20:19:00 +02:00
• c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. Marcelina Kościelnicka 2021-05-22 19:14:13 +02:00
• c7076495f1 kernel/mem: Add a check() function. Marcelina Kościelnicka 2021-05-22 16:36:50 +02:00
• ff9e0394b8 kernel/mem: defer port removal to emit() Marcelina Kościelnicka 2021-05-22 16:10:18 +02:00
• 8c734e07b8 memory_dff: Use Mem helper. Marcelina Kościelnicka 2020-10-23 17:48:00 +02:00
• 9420bde09f Run VS build on PRs and each push Miodrag Milanović 2021-05-20 19:21:34 +02:00
• 25de8faf10 Bump version Marcelina Kościelnicka 2021-05-20 12:50:32 +02:00
• 4240498f71 tests/blif: Add missing gitignore Marcelina Kościelnicka 2021-05-20 12:49:51 +02:00
• d8c5d6815c Visual Studio build action Miodrag Milanovic 2021-05-17 10:24:30 +02:00
• 34a08750fa intel_alm: Fix illegal carry chains gatecat 2021-05-15 14:40:37 +01:00
• eb106732d9 intel_alm: Add global buffer insertion gatecat 2021-05-15 14:34:48 +01:00
• 5dba138c87 intel_alm: Add IO buffer insertion gatecat 2021-05-15 14:23:22 +01:00
• 3421979f00 Change the type of current_module to Module Rupert Swarbrick 2020-04-20 14:41:55 +01:00
• 51ed4a7149 Use range-based for loop in AST::process Rupert Swarbrick 2020-04-20 16:24:57 +01:00
• 9e02786d39 Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. Adam Greig 2021-01-27 18:51:19 +00:00
• 4452080861 sv: check validity of package end label Zachary Snow 2021-05-10 11:06:02 -04:00
• 32a0ce9d68 blif: Use library cells' start_offset and upto for wideports. Marcelina Kościelnicka 2021-05-05 20:31:27 +02:00
• a6081b46ce connect: Add -assert option, fix non-working sigmap. Marcelina Kościelnicka 2021-05-05 20:32:07 +02:00
• 5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. Marcelina Kościelnicka 2021-05-04 19:14:24 +02:00
• d061b0e41a Merge pull request #2738 from mdko/xilinx-blif Miodrag Milanović 2021-04-27 11:46:41 +02:00
• 67d6f3973b Fix use of blif name in synth_xilinx command Michael Christensen 2021-04-27 02:29:52 -07:00
• 86a6ac7623 Merge pull request #2737 from YosysHQ/claire/fix2736 Claire Xen 2021-04-26 17:54:30 +02:00
• 58290c0c77 Remove duplicates from conns array in JSON front-end, fixes #2736 Claire Xenia Wolf 2021-04-26 16:31:44 +02:00
• a5adb00774 Merge pull request #2669 from YosysHQ/claire/ice40defaults Claire Xen 2021-04-21 12:24:07 +02:00
• 46d3f03d27 Add default assignments to other SB_* simulation models Claire Xenia Wolf 2021-04-20 18:52:36 +02:00
• 8aee80040d Add default assignments to SB_LUT4 Claire Xenia Wolf 2021-03-15 23:27:55 +01:00
• dce037a62c quicklogic: ABC9 synthesis Lofty 2021-04-12 10:33:40 +01:00
• a58571d0fe sf2: fix name of AND modules Stefan Riesenberger 2021-04-09 15:44:08 +02:00
• 0b05452cf7 Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memid whitequark 2021-04-09 14:22:36 +00:00
• c5c57e3f5e flatten: rewrite memid in memwr actions. whitequark 2021-04-09 09:46:53 +00:00
• 0ccc7229c0 preproc: test coverage for #2712 Zachary Snow 2021-03-30 09:38:00 -04:00
• b7ea71e6e3 equiv: Suggest running async2sync or clk2fflogic where appropriate. Marcelina Kościelnicka 2021-03-30 04:00:45 +02:00
• ba2ff1ea98 verilog: revise hot comment warnings Zachary Snow 2021-03-29 11:03:46 -04:00
• 8c5f379435 abc9: uniquify blackboxes like whiteboxes (#2695) Eddie Hung 2021-03-29 22:02:06 -07:00
• 55dc5a4e4f abc9: fix SCC issues (#2694) Eddie Hung 2021-03-29 22:01:57 -07:00
• 687f381b69 Bump version Marcelina Kościelnicka 2021-03-30 02:30:17 +02:00
• 0505c604e7 preproc: Fix up conditional handling. Marcelina Kościelnicka 2021-03-30 01:15:49 +02:00
• 1af994802e gha: trim macOS dependencies Zachary Snow 2021-03-28 17:45:38 -04:00
• e314a05e0a gha: combine jobs using matrix Zachary Snow 2021-03-28 15:28:23 -04:00
• d6d5c2ef34 rtlil: add const accessors for modules, wires, and cells Zachary Snow 2021-03-24 11:23:23 -04:00
• 4762ed90ff Merge pull request #2702 from modwizcode/patch-1 whitequark 2021-03-24 23:39:19 +00:00
• 4c39189b13 Clarify bugpoint documentation regarding output Iris Johnson 2021-03-24 16:24:33 -05:00
• c58bb1d2e1 ast: make design available to process_module() Zachary Snow 2021-03-23 12:49:11 -04:00
• 192601385f rtlil: Fix process memwr roundtrip. Marcelina Kościelnicka 2021-03-23 17:39:06 +01:00
• 049e3abf9b Merge pull request #2696 from nakengelhardt/guidelines N. Engelhardt 2021-03-23 17:41:13 +01:00
• 4a35f244aa quicklogic: Add .gitignore file for test outputs. Marcelina Kościelnicka 2021-03-23 14:51:37 +01:00
• 6b2100bf01 json: Improve the "processes in module" message a bit. Marcelina Kościelnicka 2021-03-23 14:47:32 +01:00
• d9ec35a526 split CodingReadme into multiple files N. Engelhardt 2021-03-22 19:16:25 +01:00
• 92d5550a90 verilog: check entire user type stack for type definition Xiretza 2021-03-18 21:53:02 +01:00
• 4f4e70876f sv: allow typenames as function return types Zachary Snow 2021-03-18 13:38:25 -04:00
• 6a0d1e117d Merge pull request #2681 from msinger/fix-issue2606 Miodrag Milanović 2021-03-19 08:47:07 +01:00
• 0c66141ed2 verilog: rebuild user_type_stack from globals before parsing file Xiretza 2021-03-16 16:42:14 +01:00
• 3a12617ec0 Add simple CI using github actions. Marcelina Kościelnicka 2021-03-17 19:32:50 +01:00
• 3aa10e90ba modtools: fix use-after-free of cell pointers in ModWalker Xiretza 2021-03-15 15:55:18 +01:00
• f4298b057a quicklogic: PolarPro 3 support Lofty 2021-03-17 02:34:30 +00:00
• 8740fdf1d7 ast: Use better parameter serialization for paramod names. Marcelina Kościelnicka 2021-03-17 18:30:49 +01:00
• d05d47cc04 Fix check for bad std::regex (fixes #2606) Michael Singer 2021-03-17 23:22:50 +01:00
• cae905f551 Blackbox all whiteboxes after synthesis gatecat 2021-03-17 12:16:53 +00:00
• c8b45a4a82 bugpoint: add runner option Zachary Snow 2021-03-16 10:54:22 -04:00
• f71c2dcca6 sv: carry over global typedefs from previous files Zachary Snow 2021-03-16 11:06:40 -04:00
• 092e923330 verilog: fix buf/not primitives with multiple outputs Xiretza 2021-03-17 00:18:36 +01:00
• dd6d34f461 blackbox: Include whiteboxed modules gatecat 2021-03-17 12:06:09 +00:00
• 937392ad33 Replace assert in get_reference with more useful error message Lofty 2021-03-17 02:43:25 +00:00
• 4f187d53c5 verilog: support module scope identifiers in parametric modules Zachary Snow 2021-03-04 14:07:56 -05:00
• 3d9698153f json: Add support for memories. Marcelina Kościelnicka 2021-03-09 20:42:14 +01:00
• a55bf6375b proc_arst: Add special-casing of clock signal in conditionals. Marcelina Kościelnicka 2021-03-12 17:05:39 +01:00
• 3af871f969 opt_clean: Remove init attribute bits together with removed DFFs. Marcelina Kościelnicka 2021-03-09 21:32:16 +01:00
• f965b3fa54 rtlil: Disallow 0-width chunks in SigSpec. Marcelina Kościelnicka 2021-03-09 02:54:56 +01:00
• e178d0367a Merge pull request #2658 from zachjs/parameters-across-files whitequark 2021-03-14 15:02:16 +00:00
• 640b9927fa sv: allow globals in one file to depend on globals in another Zachary Snow 2021-03-11 13:05:04 -05:00
• 396ad17e06 Merge pull request #2653 from zachjs/global-parameter whitequark 2021-03-12 01:34:06 +00:00
• feff32914b Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes whitequark 2021-03-11 20:01:10 +00:00
• cb9f3b6abf verilog: disallow overriding global parameters Zachary Snow 2021-03-11 11:49:15 -05:00
• 81c2b92bb4 Add _pm.h files to GENLIST, fixes vcxsrc target Miodrag Milanovic 2021-03-11 15:56:32 +01:00
• 83fc5cc28b Replace assert in xaiger with more useful error message Dan Ravensloft 2021-03-10 19:31:55 +00:00
• 26e01a67db Merge pull request #2643 from zachjs/fix-param-no-default-log whitequark 2021-03-08 16:36:03 -08:00
• 0b0e219765 Bump version Marcelina Kościelnicka 2021-03-08 20:18:11 +01:00
• a3528649c8 memory_dff: Remove now-useless write port handling. Marcelina Kościelnicka 2021-02-23 19:42:51 +01:00
• 89c74ffd71 verilog: Use proc memory writes in the frontend. Marcelina Kościelnicka 2021-02-23 16:48:29 +01:00
• 4e03865d5b Add support for memory writes in processes. Marcelina Kościelnicka 2021-02-23 00:21:46 +01:00
• c00a29296c sim: Avoid a crash on empty cell connection. Marcelina Kościelnicka 2021-03-01 20:01:39 +01:00
• 760284033d proc_dff: Fix emitted FF when a register is not assigned in async reset Marcelina Kościelnicka 2021-03-06 03:59:03 +01:00
• bc717abad2 memory_dff: Remove code looking for $mux cells. Marcelina Kościelnicka 2021-03-05 01:23:25 +01:00
• d555454969 tests/bram: Do not generate write address collisions. Marcelina Kościelnicka 2021-03-04 17:55:57 +01:00
• bdc4fd0e92 Fix param without default log line Zachary Snow 2021-03-07 16:06:25 -05:00
• 9cdc6b5f2e Replace assert in abc9_ops with more useful error message Dan Ravensloft 2021-03-05 22:13:15 +00:00
• ab76d9cec5 cxxrtl: don't assert on edge sync rules tied to a constant. whitequark 2021-03-07 14:29:30 +00:00
• d1de08e38a cxxrtl: allow always sync rules in debug_eval. whitequark 2021-03-07 14:28:45 +00:00
• 9bb839c613 Merge pull request #2626 from zachjs/param-no-default whitequark 2021-03-07 05:48:03 -08:00
• 72ae15c77c Merge pull request #2632 from zachjs/width-limit whitequark 2021-03-07 03:45:41 -08:00
• b1a8e73a60 sv: fix some edge cases for unbased unsized literals Zachary Snow 2021-03-03 14:36:19 -05:00
• d245e2bae5 proc_clean: Fix empty case removal conditions. Marcelina Kościelnicka 2021-03-06 11:05:57 +01:00
• 3d2aef0bde Remove a few functions that, in fact, did not exist in the first place. Marcelina Kościelnicka 2021-03-06 01:18:24 +01:00
• 55e5bd4213 Replace assert in addModule with more useful error message Dan Ravensloft 2021-03-05 21:45:11 +00:00
• 9dd813374e Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr whitequark 2021-03-05 05:30:19 -08:00
• 06da2e0f18 Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types whitequark 2021-03-05 04:57:22 -08:00
• b117f9bba8 Merge pull request #2633 from whitequark/cxxrtl-no-top whitequark 2021-03-05 04:14:07 -08:00
• 14ce8bdaa6 cxxrtl: follow aliases to outlines when emitting $memrd.ADDR. whitequark 2021-03-05 12:08:48 +00:00
• 8471808834 cxxrtl: add pass debug flag to show assigned wire types. whitequark 2021-03-05 11:44:39 +00:00