github.com/antonblanchard.chiselwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/chiselwatt.git synced 2026-03-10 20:54:08 +00:00
Code Releases Activity

Move PLLs into pll/

Browse Source 
Also rename pll_ecp5_evn.v to pll_ehxplll.v

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-02-02 09:42:15 +11:00
committed by Anton Blanchard
parent e3990af2ef
commit d0a15b35de
4 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile
View File

@@ -68,8 +68,8 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
synth: chiselwatt.bit
chiselwatt.json: $(verilog_files) insns.hex pll_ecp5_evn.v toplevel.v
$(YOSYS) -p "read_verilog -sv pll_ecp5_evn.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel"
chiselwatt.json: $(verilog_files) insns.hex pll/pll_ehxplll.v toplevel.v
$(YOSYS) -p "read_verilog -sv pll/pll_ehxplll.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel"
chiselwatt_out.config: chiselwatt.json $(LPF)
$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)

4
chiselwatt.core
View File

@@ -14,12 +14,12 @@ filesets:
cmod_a7-35:
files:
- constraints/cmod_a7-35.xdc : {file_type : xdc}
- pll_mmcme2.v : {file_type : verilogSource}
- pll/pll_mmcme2.v : {file_type : verilogSource}
ecp5-evn:
files:
- constraints/ecp5-evn.lpf : {file_type : LPF}
- pll_ecp5_evn.v : {file_type : verilogSource}
- pll/pll_ehxplll.v : {file_type : verilogSource}
targets:
cmod_a7-35:

0
pll_ecp5_evn.v → pll/pll_ehxplll.v
View File

0
pll_mmcme2.v → pll/pll_mmcme2.v
View File