This PR adds support for Polarfire FPGA from Microchip/Microsemi.
The support has also been added to Fusesoc .core file to use the
soon-to-be merged Libero backend.
- Due to a tool incompatibility, Libero does not accept a module
named "pll". Due to this, I've renamed the PLLs to Chiselwatt_pll.
- Fixed formatting for chiselwatt.core file according to YAML lexer.
- Added micropython and helloworls filesets to .core so it's possible to
override the .hex to be used on core generation.
Demo of hello_world and Micropython:
https://twitter.com/carlosedp/status/1362119833324826626
Signed-off-by: Carlos de Paula <me@carlosedp.com>
