Improved build instructions by using Fusesoc as package manager and
multi-target toolchain.
Updated hello_world sample app to fetch clock from SYSCON registers.
Rebuilt all sample applications based on latest version and using SYSCON
Improve Makefile build process for samples.
Signed-off-by: Carlos de Paula <me@carlosedp.com>
This PR adds support for Polarfire FPGA from Microchip/Microsemi.
The support has also been added to Fusesoc .core file to use the
soon-to-be merged Libero backend.
- Due to a tool incompatibility, Libero does not accept a module
named "pll". Due to this, I've renamed the PLLs to Chiselwatt_pll.
- Fixed formatting for chiselwatt.core file according to YAML lexer.
- Added micropython and helloworls filesets to .core so it's possible to
override the .hex to be used on core generation.
Demo of hello_world and Micropython:
https://twitter.com/carlosedp/status/1362119833324826626
Signed-off-by: Carlos de Paula <me@carlosedp.com>
Added hello_world sources and new Makefile targets for building
hello_world and Micropython inside containers.
Updated documentation reflecting these changes and moved binaries
to ./samples/binaries/.
Signed-off-by: Carlos de Paula <me@carlosedp.com>
make check has stopped working recently:
java.lang.ClassCastException: java.lang.Class cannot be cast to firrtl.options.Dependency
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
at scala.collection.immutable.List.foldLeft(List.scala:89)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$_targets(DependencyManager.scala:34)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$_targets$(DependencyManager.scala:33)
at firrtl.options.PhaseManager.firrtl$options$DependencyManager$$_targets$lzycompute(DependencyManager.scala:414)
at firrtl.options.PhaseManager.firrtl$options$DependencyManager$$_targets(DependencyManager.scala:414)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$prerequisiteGraph(DependencyManager.scala:115)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$prerequisiteGraph$(DependencyManager.scala:113)
at firrtl.options.PhaseManager.firrtl$options$DependencyManager$$prerequisiteGraph$lzycompute(DependencyManager.scala:414)
I need to investigate, but setting chisel3 to 3.2.5 fixes it for now.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Added a couple of improvements to the Makefile and Readme:
* Restructured the Makefile to support multiple boards based on variable
* Verilator build is also done in Docker container with local option
* Restructured Readme to reflect changes in the Makefile
* Support for running the verilator chiselwatt binary in a Docker
container in case the OS is not Linux.
Signed-off-by: Carlos de Paula <me@carlosedp.com>
For simplicity we originally made loads and stores slow instructions. We
now want to integrate them into the fast pipeline, so add a new cycle to
the pipeline (called memory).
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This adds support for the cheap Colorlight 5A-75B ECP5 based board.
UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.
All the I/Os on this board go through bidirectional level shifters that
appear to be hardwired as outputs. To get an input pin for UART RX, we
use the button I/O which is also routed to connector J19. The downside is
we can't use the button for reset.
One potential issue is that UART TX is 5V but UART RX is 3.3V. To keep
the FPGA happy any attached UART chip needs to output 3.3V, but it also
needs to be 5V tolerant to handle the level shifted input.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
