github.com/antonblanchard.chiselwatt
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18 Commits 12 Branches 0 Tags
737ba98e02968fafbaa199526d77a59de982059f
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5 Commits

Author SHA1 Message Date
Anton Blanchard
737ba98e02 Move some of the CR handling into its own unit 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 21:01:15 +11:00
Anton Blanchard
63ed617cb6 Remove SystemVerilog syntax 
Lattice Diamond doesn't seem to support SystemVerilog which is a bit
depressing. We only use the syntax in a few places, so fix that up.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-31 02:49:26 +11:00
Anton Blanchard
1aeb5dad28 Remove an unused bit from the Divider 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-30 18:23:01 +11:00
Anton Blanchard
08ca3da14e Remove some old tests 
These modules aren't used any more.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2020-01-30 18:11:46 +11:00
Anton Blanchard
f138ab7c7c Initial import 2020-01-30 05:20:07 +11:00