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Mono Color

• 0832fed06c Merge pull request #22 from antonblanchard/store-fix Anton Blanchard 2019-09-08 16:23:54 +10:00
• 021d427d3f Stores need to wait for wishbone write ack Anton Blanchard 2019-09-08 16:00:36 +10:00
• c64bf23c1a Merge pull request #21 from antonblanchard/xdc-update Anton Blanchard 2019-09-08 10:19:29 +10:00
• 63295526ad Add CONFIG_VOLTAGE and CFGBVS entries Anton Blanchard 2019-09-08 09:49:39 +10:00
• 03fd06deaf Rework SOC reset Anton Blanchard 2019-09-07 21:28:21 +10:00
• a53ad60014 Rename a few reset signals Anton Blanchard 2019-09-07 21:08:02 +10:00
• e39400681b Merge pull request #18 from mikey/verific Anton Blanchard 2019-09-06 20:54:50 +10:00
• 83d773090e Fix verific script with new VHDL files Michael Neuling 2019-09-06 15:05:01 +10:00
• a15eb4e28d Merge pull request #17 from antonblanchard/writeback-signal Anton Blanchard 2019-09-06 10:09:26 +10:00
• 147b259691 Use a better input signal in writeback Anton Blanchard 2019-09-06 09:46:55 +10:00
• 3f59396907 Merge pull request #16 from antonblanchard/decode2_rework2 Anton Blanchard 2019-09-04 06:33:40 +10:00
• 5e140298a5 Rework decode2 Anton Blanchard 2019-09-03 12:44:03 +10:00
• d1fdc286c4 Merge pull request #13 from mikey/dynamic-ranges Anton Blanchard 2019-08-31 13:34:38 +10:00
• 4d5abfb430 Remove dynamic ranges from code Michael Neuling 2019-08-29 09:47:45 +10:00
• 7a85e3877d Merge pull request #10 from antonblanchard/arty-fix Anton Blanchard 2019-08-30 09:06:48 +10:00
• 5379b805ec Arty A7 reset pin is C2 Anton Blanchard 2019-08-30 08:39:44 +10:00
• 3819768d2a Merge pull request #7 from riktw/fusesoc_arty_a7 Anton Blanchard 2019-08-30 08:38:13 +10:00
• 5aba4e7346 Merge pull request #9 from antonblanchard/travis-fix Anton Blanchard 2019-08-30 08:26:35 +10:00
• 6c8d28a642 A few Travis CI fixes Anton Blanchard 2019-08-30 08:12:54 +10:00
• 4ebd6fc1f7 Added support for building for Arty A7 boards riktw 2019-08-27 22:20:02 +02:00
• f98370f9e6 Merge pull request #5 from antonblanchard/travis-test Anton Blanchard 2019-08-29 07:46:51 +10:00
• 2ee269abdb Add an initial travis.yml Anton Blanchard 2019-08-27 10:40:43 +10:00
• 0fd18c2455 Add srd and srw Anton Blanchard 2019-08-28 14:50:11 +10:00
• 73daacbcd4 Add sim only divw Anton Blanchard 2019-08-28 14:07:29 +10:00
• 95b9f19882 Fix ghdl build error with pp_soc_memory Anton Blanchard 2019-08-27 22:12:33 +10:00
• 1fa0b332ca micropython only requires 512kB of BRAM Anton Blanchard 2019-08-27 12:02:00 +10:00
• 1aadee281d Merge pull request #6 from mikey/gif Anton Blanchard 2019-08-27 11:50:25 +10:00
• 96787091a6 Add -Wall to CFLAGS Anton Blanchard 2019-08-27 11:44:34 +10:00
• d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md Michael Neuling 2019-08-27 11:19:15 +10:00
• 7277c6b5ab Add missing argument to fprintf warning Anton Blanchard 2019-08-26 23:11:51 +10:00
• 77f1588a7f Add some initial FPGA synthesis instructions Anton Blanchard 2019-08-26 22:32:15 +10:00
• 0a0ad9b384 Rebuild hello world assuming a 50MHz clock Anton Blanchard 2019-08-26 12:33:15 +10:00
• c036363d8f Merge pull request #3 from olofk/plle2 Anton Blanchard 2019-08-26 22:02:17 +10:00
• 12327034d6 Add and use plle2 primitive for nexys boards Olof Kindgren 2019-08-24 11:25:21 +02:00
• 5b2984a15d Merge pull request #4 from sharkcz/build Anton Blanchard 2019-08-26 11:33:38 +10:00
• 2d7994dc12 don't cross compile when on Power Dan Horák 2019-08-24 14:02:35 +02:00
• 8bc3e8ea0a Add a simple hello_world example that also echos input Anton Blanchard 2019-08-24 08:59:17 +10:00
• 01e6b8f583 Merge pull request #2 from olofk/fusesoc_nexys_a7 Anton Blanchard 2019-08-24 05:25:48 +10:00
• b9bf19f912 Added synthesis target Olof Kindgren 2019-08-23 14:20:20 +02:00
• 250d09ed2d Add Nexys Video support Olof Kindgren 2019-08-23 14:09:06 +02:00
• 5e56b14125 Add FuseSoC core description file with Nexys A7 support Olof Kindgren 2019-08-23 13:32:05 +02:00
• abca85b034 Add constraint file for Nexys A7 Olof Kindgren 2019-08-23 13:19:11 +02:00
• e8ad9bed10 Expose ram init file and memory size through toplevel Olof Kindgren 2019-08-23 13:18:39 +02:00
• b5bccc4c13 Add dummy clock generator Olof Kindgren 2019-08-23 13:17:35 +02:00
• 37fe8b954c Add a few more FPGA related files Anton Blanchard 2019-08-23 16:23:53 +10:00
• 5a29cb4699 Initial import of microwatt Anton Blanchard 2019-08-22 16:46:13 +10:00