antonblanchard.microwatt

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4d0afa3a6d Reformat CR file Anton Blanchard 2019-09-19 20:22:36 +10:00
4d9b2a1165 Reformat register file Anton Blanchard 2019-09-19 20:21:58 +10:00
8dd97fbe7f Reformat multiply code Anton Blanchard 2019-09-19 20:19:46 +10:00
99dd4de54e Don't use VHDL 2008 condition operator in multiply Anton Blanchard 2019-09-19 20:18:01 +10:00
550b2b8608 Merge pull request #62 from antonblanchard/byte-reverse-store-opt Anton Blanchard 2019-09-16 13:17:37 +10:00
135805d2ac Merge pull request #61 from antonblanchard/execute-cleanup Anton Blanchard 2019-09-16 13:14:25 +10:00
a061924a78 Move byte reversal of stores to first cycle Anton Blanchard 2019-09-16 11:49:44 +10:00
6d85920068 execute1 no longer needs sim_console Anton Blanchard 2019-09-16 11:18:53 +10:00
a4c8dd860a Merge pull request #60 from antonblanchard/testbenches Anton Blanchard 2019-09-15 22:52:14 +10:00
1b6eef2a5d Fix multiply_tb Anton Blanchard 2019-09-13 20:35:08 +10:00
1e3e16e500 Add an icache testbench Anton Blanchard 2019-09-13 20:17:17 +10:00
d573748da0 Merge pull request #56 from antonblanchard/writeback-fix3 Anton Blanchard 2019-09-15 22:08:57 +10:00
152261fac8 Remove cycle in writeback Anton Blanchard 2019-09-15 18:03:48 +10:00
7bb88d5321 Merge pull request #59 from antonblanchard/trap-decode Anton Blanchard 2019-09-15 21:37:47 +10:00
f5a5b91736 Merge pull request #58 from antonblanchard/decode2-assert Anton Blanchard 2019-09-15 21:30:30 +10:00
427effdaa9 Fix make check Anton Blanchard 2019-09-15 21:21:36 +10:00
d813ffb748 Fix spurious outstanding assert Anton Blanchard 2019-09-15 18:59:24 +10:00
30aa16d8f3 Merge pull request #57 from antonblanchard/add-nop Anton Blanchard 2019-09-15 18:34:27 +10:00
9867fb6149 Add a decode for the nop instruction Anton Blanchard 2019-09-15 18:18:24 +10:00
85062793b1 Merge pull request #55 from antonblanchard/fetch-fix Anton Blanchard 2019-09-15 11:18:42 +10:00
d52046104f Add a default value for RESET_ADDRESS Anton Blanchard 2019-09-15 10:25:57 +10:00
71e45a82ee Merge pull request #51 from antonblanchard/writeback-fix Anton Blanchard 2019-09-15 09:55:10 +10:00
e69e79d8af Reformat writeback.vhdl Anton Blanchard 2019-09-15 09:07:34 +10:00
50a361a5dc Exit if we try to write more than one GPR or CR in a cycle Anton Blanchard 2019-09-15 09:04:47 +10:00
ab34c48392 Merge pull request #50 from antonblanchard/decode1-opt Anton Blanchard 2019-09-12 21:15:24 +10:00
acdb2ea157 No need to gate nia or insn in decode1 Anton Blanchard 2019-09-12 17:06:09 +10:00
986881f258 Add a patch to route the NIA out to GPIOs nia-debug Anton Blanchard 2019-09-11 15:43:49 +10:00
0e6861e5db Merge pull request #49 from antonblanchard/icache-2 Anton Blanchard 2019-09-12 16:14:28 +10:00
89849a6856 Add a simple direct mapped icache Anton Blanchard 2019-09-11 13:05:17 +10:00
6cbf456388 SOC memory wishbone should clear ACK regardless of STB Anton Blanchard 2019-09-11 17:21:52 +10:00
67446709ca Merge pull request #48 from antonblanchard/clk_gen_bypass Anton Blanchard 2019-09-12 13:03:33 +10:00
d89a9929fd Fix clk_gen_bypass Anton Blanchard 2019-09-12 12:25:18 +10:00
80aa781454 Merge pull request #47 from antonblanchard/if-fix Anton Blanchard 2019-09-12 09:46:22 +10:00
ca6f84efd6 Merge pull request #46 from antonblanchard/record-fix Anton Blanchard 2019-09-12 09:46:01 +10:00
b9e28598b4 Explicitly check against '1' in if statements Anton Blanchard 2019-09-12 09:19:31 +10:00
142a722ce4 Remove names from end record statements Anton Blanchard 2019-09-12 09:04:02 +10:00
43f81773b4 Merge pull request #45 from antonblanchard/fixes Anton Blanchard 2019-09-11 22:53:47 +10:00
7caf71ba71 Fix issue in loadstore1 Anton Blanchard 2019-09-11 22:40:53 +10:00
95442cd62c Fix issue in execute2 Anton Blanchard 2019-09-11 22:39:30 +10:00
1ba84b56dd Merge pull request #44 from antonblanchard/nia-remove Anton Blanchard 2019-09-11 21:58:01 +10:00
1d00c75ecc Remove nia from loadstore and multiply Anton Blanchard 2019-09-11 21:42:37 +10:00
8b88e26ece Merge pull request #43 from mikey/trivial Anton Blanchard 2019-09-11 21:42:00 +10:00
1e1b799382 Remove FIXME comment Michael Neuling 2019-09-11 16:50:57 +10:00
ff1455dea6 Merge pull request #41 from mikey/travis Anton Blanchard 2019-09-11 16:05:05 +10:00
2f3ca35a6e Merge pull request #42 from antonblanchard/fetch-rework-v2 Anton Blanchard 2019-09-11 16:04:10 +10:00
4528ef2b43 Reformat core.vhdl Anton Blanchard 2019-09-11 07:55:35 +10:00
a2df2a10a2 Remove sim console Anton Blanchard 2019-09-11 07:16:56 +10:00
68533c4cfb Reduce multiply to 2 cycles Anton Blanchard 2019-09-10 16:22:58 +10:00
9fe8d211eb Register outputs on writeback Anton Blanchard 2019-09-10 16:04:39 +10:00
c7aa683ba8 Register outputs on execute2 Anton Blanchard 2019-09-10 15:40:20 +10:00
819f820090 Register outputs on loadstore1 Anton Blanchard 2019-09-10 15:39:50 +10:00
a8f8c54b77 Move debug execute output into decode2 Anton Blanchard 2019-09-10 15:02:18 +10:00
92a7152370 Rework pipeline, add stall and flush signals Anton Blanchard 2019-09-04 09:36:30 +10:00
6b06d5f67d Allow a full make check on Travis Michael Neuling 2019-09-11 10:18:19 +10:00
3b32abcb5d Merge pull request #40 from antonblanchard/makefile-dependencies Anton Blanchard 2019-09-11 07:48:19 +10:00
b6b2c78163 Update Makefile dependencies Anton Blanchard 2019-09-11 07:32:00 +10:00
d3acb5cce9 Switch soc to use std_ulogic Benjamin Herrenschmidt 2019-09-10 16:59:10 +01:00
3ac1dbc737 Share soc.vhdl between FPGA and sim Benjamin Herrenschmidt 2019-09-10 16:40:11 +01:00
d21ef5836d Pass wishbone record to bram memory module Benjamin Herrenschmidt 2019-09-10 16:39:52 +01:00
1d66e1f981 Rework wishbone slave address decoding Benjamin Herrenschmidt 2019-09-10 14:52:23 +01:00
c97b080d8c Move wishbone arbiter out of the core Benjamin Herrenschmidt 2019-08-31 18:54:58 +10:00
310a56c076 Re-indent and reformat soc.vhdl Benjamin Herrenschmidt 2019-09-10 13:01:17 +01:00
a69a93b466 Split FPGA toplevel from soc Benjamin Herrenschmidt 2019-09-10 12:45:33 +01:00
5ee86e7621 Merge pull request #39 from antonblanchard/no-x-state Anton Blanchard 2019-09-10 17:07:09 +10:00
dce2e06f4c Don't send out X state from the memory behavioural Anton Blanchard 2019-09-10 16:46:41 +10:00
c3a5782bf4 Merge pull request #36 from mikey/gitignore Anton Blanchard 2019-09-10 16:31:37 +10:00
419b95a447 Merge pull request #38 from antonblanchard/multiply-warn Anton Blanchard 2019-09-10 16:31:08 +10:00
a22afbdb5b Quieten multiply warning Anton Blanchard 2019-09-10 15:31:54 +10:00
5ae92a721f Add new files to git ignore Michael Neuling 2019-09-10 15:00:35 +10:00
d79c994158 Merge pull request #35 from antonblanchard/multiply-opt Anton Blanchard 2019-09-10 09:14:31 +10:00
18b9b39a2c Simplify multiply Anton Blanchard 2019-09-08 11:11:15 +10:00
47f39440f2 Merge pull request #34 from antonblanchard/decode-table Anton Blanchard 2019-09-10 08:09:48 +10:00
9687034d78 Add a decode bit to mark an instruction as single through the pipeline Anton Blanchard 2019-09-02 16:11:31 +10:00
b0ade2857f decode1 array fix header Benjamin Herrenschmidt 2019-09-03 08:44:01 +10:00
a9065796ad Merge pull request #33 from antonblanchard/cr-fix Anton Blanchard 2019-09-09 22:44:34 +10:00
e0dfb3dce1 Merge pull request #32 from antonblanchard/register-file-forwarding Anton Blanchard 2019-09-09 22:21:30 +10:00
8bfd6e5eae Use simulated UART in core test bench Benjamin Herrenschmidt 2019-08-28 00:09:45 +10:00
1b9c6f4647 Make sim poll non-blocking Benjamin Herrenschmidt 2019-08-28 00:09:24 +10:00
48b689b665 Add simulated UART design Benjamin Herrenschmidt 2019-08-28 00:08:54 +10:00
9cbdecb561 Fix CR forwarding Anton Blanchard 2019-09-09 22:16:11 +10:00
79a14c8e37 Add forwarding in the register file Anton Blanchard 2019-09-09 16:36:47 +10:00
2241b71674 Merge pull request #31 from antonblanchard/no-second-write-port-2 Anton Blanchard 2019-09-09 16:12:59 +10:00
045a00c5d7 Merge pull request #30 from antonblanchard/writeback-assert Anton Blanchard 2019-09-09 16:12:39 +10:00
31a6fb6ef5 More second write port removal Anton Blanchard 2019-09-09 16:00:49 +10:00
fa04936c92 Add some assertions to writeback Anton Blanchard 2019-09-09 15:54:09 +10:00
4c872619b3 Merge pull request #29 from antonblanchard/no-second-write-port Anton Blanchard 2019-09-09 15:51:34 +10:00
f384f504a1 Merge pull request #28 from antonblanchard/loadstore-cleanup Anton Blanchard 2019-09-09 15:50:46 +10:00
fb4cad6eaf Remove second write port Anton Blanchard 2019-09-09 15:18:09 +10:00
aee5fded44 Remove some more loadstore debug Anton Blanchard 2019-09-09 15:03:06 +10:00
ff9070d727 Merge pull request #27 from antonblanchard/fix-cr Anton Blanchard 2019-09-09 13:35:12 +10:00
0254e40685 Fix issues with CR rework Anton Blanchard 2019-09-09 13:03:27 +10:00
b8d93728d7 Merge pull request #26 from antonblanchard/silence-loadstore-debug Anton Blanchard 2019-09-09 11:42:55 +10:00
a1ab1d3e56 Merge pull request #25 from antonblanchard/register_file_printing Anton Blanchard 2019-09-09 11:42:41 +10:00
a5d31bb554 Merge pull request #24 from antonblanchard/cr_file_cleanup Anton Blanchard 2019-09-09 11:41:44 +10:00
5d82af5204 Silence some loadstore related debug Anton Blanchard 2019-09-09 11:23:29 +10:00
04eb9583e6 Clean up register read debug output Anton Blanchard 2019-09-09 11:18:26 +10:00
9fbaea6f08 Rework CR file and add forwarding Anton Blanchard 2019-09-09 09:32:08 +10:00
7c2a2b7414 Merge pull request #19 from antonblanchard/cmod-a7 Anton Blanchard 2019-09-08 18:04:38 +10:00
270d7b1b9a Cmod A7-35 support Anton Blanchard 2019-09-06 16:24:16 +10:00
14da542d4a Merge pull request #20 from antonblanchard/reset-rework2 Anton Blanchard 2019-09-08 16:34:10 +10:00

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