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mirror of https://github.com/antonblanchard/microwatt.git synced 2026-01-24 19:21:49 +00:00
Paul Mackerras 1587d9e6eb dcache: Fix obscure bug and minor cleanups
The obscure bug is that a non-cacheable load with update would never
do the update and would never complete the instruction.  This is fixed
by making state NC_LOAD_WAIT_ACK go to LOAD_UPDATE2 if r1.req.update
is set.

The slow load forms with update can go to LOAD_UPDATE2 at the end
rather than LOAD_UPDATE, thus saving a cycle.  Loads with a cache
hit need the LOAD_UPDATE state in the third cycle since they are
not writing back until the 4th cycle, when the state is LOAD_UPDATE2.
Slow loads (cacheable loads that miss and non-cacheable loads)
currently go to LOAD_UPDATE in the cycle after they see
r1.wb.ack = 1 for the last time, but that cycle is the cycle where
they write back, and the following cycle does nothing.  Going to
LOAD_UPDATE2 in those cases saves a cycle and makes them consistent
with the load hit case.

The logic in the RELOAD_WAIT_ACK case doesn't need to check
r1.req.load = '1' since we only ever use RELOAD_WAIT_ACK for loads.

There are also some whitespace fixes and a typo fix.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-02-21 12:34:23 +11:00
2020-01-19 18:17:15 +11:00
2019-10-08 21:02:46 -07:00
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2019-09-19 20:33:58 +10:00
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2019-10-30 13:18:58 +11:00
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Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)
Description
A tiny Open POWER ISA softcore written in VHDL 2008
Readme 75 MiB
Languages
Verilog 79.8%
VHDL 14.8%
C 3.2%
Tcl 1.1%
Assembly 0.6%
Other 0.4%