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Some more Chip fastpath stability stuff

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This commit is contained in:
beeanyew
2021-08-11 14:18:40 +02:00
parent 78f2b53645
commit eea4bcfafa
2 changed files with 9 additions and 1 deletions
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3
emulator.c
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@@ -231,7 +231,8 @@ cpu_loop:
}
if (last_irq != 0 && last_irq != last_last_irq) {
last_last_irq = last_irq;
M68K_SET_IRQ(last_irq);
if (ipl_enabled[last_irq])
M68K_SET_IRQ(last_irq);
}
m68k_execute(state, 50);
}

7
gpio/ps_protocol.c
View File

@@ -236,6 +236,7 @@ void ps_write_status_reg(unsigned int value) {
*(gpio + 7) = 1 << PIN_WR; // delay
#ifdef CHIP_FASTPATH
*(gpio + 7) = 1 << PIN_WR; // delay 210810
*(gpio + 7) = 1 << PIN_WR; // delay 210810
#endif
*(gpio + 10) = 1 << PIN_WR;
*(gpio + 10) = 0xffffec;
@@ -246,7 +247,9 @@ void ps_write_status_reg(unsigned int value) {
}
unsigned int ps_read_status_reg() {
GPFSEL_OUTPUT;
*(gpio + 7) = (REG_STATUS << PIN_A0);
*(gpio + 7) = 1 << PIN_RD;
*(gpio + 7) = 1 << PIN_RD;
*(gpio + 7) = 1 << PIN_RD;
@@ -254,8 +257,12 @@ unsigned int ps_read_status_reg() {
#ifdef CHIP_FASTPATH
*(gpio + 7) = 1 << PIN_RD; // delay 210810
*(gpio + 7) = 1 << PIN_RD; // delay 210810
*(gpio + 7) = 1 << PIN_RD; // delay 210810
*(gpio + 7) = 1 << PIN_RD; // delay 210810
#endif
GPFSEL_INPUT;
unsigned int value = *(gpio + 13);
while ((value=*(gpio + 13)) & (1 << PIN_TXN_IN_PROGRESS)) {}