beeanyew
9b1031c859
Fix Musashi compilation with prefetch emulation disabled
2021-06-27 19:20:22 +02:00
beeanyew
77a6ed0756
Actually remove the read/write ranges "properly"
2021-06-23 04:52:44 +02:00
beeanyew
16a902fad2
Add some more Mac68k handling stuff
2021-06-23 04:42:58 +02:00
Rune Holm
747b19f7c8
removed most traces of direct access to the m68ki_cpu global variable
2021-06-20 21:42:03 +01:00
Rune Holm
0c763fca70
introducing CPU state parameter 5 - now switched most register state over
2021-06-20 21:42:03 +01:00
Rune Holm
514f1d4e24
introducing CPU state parameter 4
2021-06-20 21:41:55 +01:00
Rune Holm
d06400230f
introducing CPU state parameter 3
2021-06-20 21:35:37 +01:00
Rune Holm
6d74804193
introducing CPU state paramter 2
2021-06-20 21:54:08 +02:00
Rune Holm
14636790c6
introducing CPU state parameter
2021-06-20 21:54:05 +02:00
Rune Holm
18cba7ddc6
step 1: add a state parameter to all opcode functions
2021-06-20 21:50:15 +02:00
Rune Holm
a2b0521dbd
move address translation cache fields from global variables to the m68k struct, as
...
this way we can pass around one pointer and access them all in the future.
This happens to win 5-10% performance, because now the code generator can generate a single
global variable pointer to get to all of the translation cache/range fields at once.
2021-06-18 22:01:22 +01:00
Rune Holm
b91e0e809d
optimise away an unnecessary subtract on the instruction fetch fast path
2021-06-18 22:01:20 +01:00
beeanyew
a48402ce6c
Fix Musashi compilation with prefetch emulation disabled
2021-06-18 22:01:17 +01:00
beeanyew
c1603ffb07
Restore missing lines to m68kcpu.c
2021-06-11 21:47:27 +02:00
beeanyew
62d18f9f13
Merge branch 'wip-crap' into main
2021-06-11 21:38:36 +02:00
Rune Holm
fe3b4bb032
pull the PC masking into the code translation cache, so that we only need to mask the PC on our slow path. Gives us another 5-10% speedup.
2021-06-11 19:34:03 +01:00
Rune Holm
3203ac8590
Created address translation fast path for code reads, separated slow path into separate function so the fast path is more likely to be inlined. 10-20% performance improvement
2021-06-11 18:37:57 +01:00
beeanyew
8a14e4c1a1
Add not-so-simple config switching from Amiga side
2021-04-23 13:03:54 +02:00
shanshe
75bbc70be8
Reset from Amiga CTRL+A+A
2021-04-13 21:53:44 +02:00
shanshe
b2121be23f
Bus Error and 68k OPs update (to latest MAME)
2021-04-13 18:31:06 +02:00
shanshe
e48448eff9
MMU and InstructionCache update (MAME's latest code)
2021-04-13 10:32:30 +02:00
shanshe
6c9276f882
FPU update as latest MAME
2021-04-13 10:00:48 +02:00
beeanyew
1f804c7e36
[WIP] IRQ experiments, revert Musashi speed hax for now
2021-03-08 15:53:23 +01:00
beeanyew
60acb37185
Certified Musashi speed hax
...
Probably requires a make clean due to things being in header files.
2021-02-18 05:29:59 +01:00
beeanyew
0d0bb0355d
[WIP] PiSCSI boot ROM experiments
2021-01-29 01:37:40 +01:00
beeanyew
2e76e75128
Some Musashi mapping and RTG fixes/debug
2021-01-06 13:13:05 +01:00
beeanyew
2eb8474c92
Plug some read/write mappings directly into Musashi
2020-12-31 12:15:42 +01:00
Claude
e2f86a9c1a
first commit
2020-10-31 09:26:56 +01:00
