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9 Commits

Author SHA1 Message Date
J
f16479b668 some more instruction colation 2019-09-26 21:15:44 -04:00
JnR
ff3e286289 Start to simplify the staircase decoder 2019-09-25 22:19:31 -04:00
J
e661848e58 Change back to complete ROM tests. NOTE: may overflow FPGA 2019-09-22 23:06:25 -04:00
J
5825a157cf Cosmetic... print key names. RAM full, use rev 28 for block ram checking instead 2019-04-01 17:45:50 -04:00
J
07025535a6 merge 2019-03-30 00:14:00 -04:00
J
cc164bb8b6 Link order matters? Yes, yes it does... 2019-03-30 00:12:12 -04:00
J
d21f78598e With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct. 2019-03-25 21:50:49 -04:00
J
07afa61fa1 Drives LCD with ASCII renderer. Split main.c off for 42s 2019-03-18 17:39:56 -04:00
J
9e5f83edd9 Add in the test rom 2019-03-03 19:35:20 -05:00