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  • fe265519e2 Add some comments. master Rob Landley 2019-12-07 22:22:19 -06:00
  • 7508f960ce Remove some files not used in this SoC from the analysis stage. Rob Landley 2019-12-07 22:20:16 -06:00
  • 11c1ba7c5a Separate out predecoder. (Mostly Jeff's work.) Rob Landley 2019-11-15 02:21:29 -06:00
  • c4ac0a6e0e Shuffle types around more logically, add comments, split pkg/body builds. Rob Landley 2019-11-15 01:41:16 -06:00
  • 25a45b1c3c Move datapath_reg_t to datapath_pkg instead of components_pkg. Rob Landley 2019-11-15 00:44:16 -06:00
  • 4bd610bde9 Add some comments, and don't make "how many bits in a 32 bit cpu" a define. Rob Landley 2019-11-15 00:36:47 -06:00
  • 9403c12f9d Rename things to avoid "hides" warnings. Rob Landley 2019-11-12 06:16:14 -06:00
  • 60e396e96f Remove more warnings (name conflicts within overlapping scope). Rob Landley 2019-11-12 05:45:30 -06:00
  • 0f95035660 Remove one warning, re-wordwrap, add comment with paper behind shifter. Rob Landley 2019-11-12 04:46:53 -06:00
  • 0340edd4d2 Add comments and progress output to build script, cut simulation timeout in half (ROM finishes in 0.7ms, don't need 2ms run). Rob Landley 2019-11-11 05:40:40 -06:00
  • 429b6fa326 Add a README. Rob Landley 2019-11-11 05:25:45 -06:00
  • c7cf985e9b Whitespace: Redo indentation and tweak comments slightly. Rob Landley 2019-11-10 21:01:26 -06:00
  • d053118e47 Put rn and rm in variables. Rob Landley 2019-11-10 01:41:52 -06:00
  • 986651bd71 Comment out more default values, and switch defaults to most common entry. Rob Landley 2019-11-09 08:58:20 -06:00
  • 253119d8b3 Comment out lines redundantly setting signals to their default value. Rob Landley 2019-11-09 02:44:44 -06:00
  • 662a203727 Change run script to work with ghdl mcode instead of llvm backend, add comment about the difference. Rob Landley 2019-11-04 18:13:43 -06:00
  • 4caf1245aa MOVA, (aka LEA) collapsed JnR 2019-09-27 18:14:15 -04:00
  • 74b84b6bff more MOV instructions collapsed JnR 2019-09-27 17:02:58 -04:00
  • f16479b668 some more instruction colation J 2019-09-26 21:15:44 -04:00
  • 4b3f730f84 pre classify fcn. begin to refactor decode JnRnJ 2019-09-26 16:24:03 -04:00
  • ff3e286289 Start to simplify the staircase decoder JnR 2019-09-25 22:19:31 -04:00
  • 7eb65c56eb The control registers moved in the register file a while back and no longer need an extra wait state to access, so make STC.L work like STS.L. Rob Landley 2019-09-23 18:19:24 -05:00
  • e661848e58 Change back to complete ROM tests. NOTE: may overflow FPGA J 2019-09-22 23:06:25 -04:00
  • 1fd2181c34 Add the staircase decoder version back in J 2019-09-22 18:43:43 -04:00
  • 23c9b785f2 Clean up data and instruction bus, and decoders. Hand hacked, should be auto gen J 2019-04-02 22:23:49 -04:00
  • 3ca89bdbd0 Remove hack to work around incomplete pipeline reset due to Lattice tools, fixed by reset generator J 2019-04-02 21:11:55 -04:00
  • d28a771f6d Add reset generator to work around Lattice ignoring reset values. Fixes ROM decoder, reduce logic size by 8.5% J 2019-04-02 17:52:39 -04:00
  • 53246c4690 Bring over ROM decoder version. Sim is correct, synth is 10% smaller doesn't boot. This CPU corresponds ~rev 745:b529b2d1c276 of SEI internal repos soc_top/components/cpu J 2019-04-02 16:18:02 -04:00
  • 5825a157cf Cosmetic... print key names. RAM full, use rev 28 for block ram checking instead J 2019-04-01 17:45:50 -04:00
  • 6acf3a811c All keys work. First 'scan' algorithm. Precharge timing needs tuning J 2019-03-31 02:10:36 -04:00
  • e14eca18c0 CPU comes up. Lattice SPR works. LCD works. J 2019-03-30 17:21:02 -04:00
  • 07025535a6 merge J 2019-03-30 00:14:00 -04:00
  • cc164bb8b6 Link order matters? Yes, yes it does... J 2019-03-30 00:12:12 -04:00
  • 3ec7c27f36 Continue simple cleanups of pinouts and platform split. Still doesn't work, though J 2019-03-27 21:04:53 -04:00
  • 4d896e726c Minor change to pinouts for v1.1 board J 2019-03-26 12:05:44 -04:00
  • d21f78598e With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct. J 2019-03-25 21:50:49 -04:00
  • 520a01319c Free42 / up5k top level sim driver script J 2019-03-19 16:45:37 -04:00
  • f7ad4be38a Finish Free42 pinout. First synth with all pins. Seems to break LCD? J 2019-03-19 16:44:01 -04:00
  • bcd796f196 Add pinout constraints for 42s J 2019-03-18 17:41:13 -04:00
  • 07afa61fa1 Drives LCD with ASCII renderer. Split main.c off for 42s J 2019-03-18 17:39:56 -04:00
  • 2246a52244 Work around strange %pr bug in entry.c. Finally runs to C code J 2019-03-17 17:03:19 -04:00
  • d6d809c516 Attempt to avoid write conflict on Lattice EB RAM J 2019-03-15 16:46:15 -04:00
  • beada4032f Add simulation stuff for register file J 2019-03-14 22:56:02 -04:00
  • 2f0f7d2797 A few warnings fixed J 2019-03-13 19:40:04 -04:00
  • c611736bad Sync RAM register file implemntation J 2019-03-13 17:05:56 -04:00
  • fb8fdd41c7 move back to ghdl because nvc can't trace records yet, even though it simulates them J 2019-03-12 22:42:41 -04:00
  • 93d011ba48 Add sim by default and wave viewer ctl file for reg file debug J 2019-03-08 01:37:20 -05:00
  • d94eb15232 Actually add sim model for Lattice HF clk J 2019-03-08 01:10:20 -05:00
  • dfd7c38c98 Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk J 2019-03-08 01:09:52 -05:00
  • 480c4cefe0 Pin mapping for EVB J 2019-03-05 22:55:59 -05:00
  • f0dbd0a33e correct outputs for Lattice EVB. Fix stack location. Still crashes with result code 0x11 on the LEDs J 2019-03-05 02:17:06 -05:00
  • b1176ec9aa First synthesys for ICE40 UP5k with everything to blink LEDs J 2019-03-04 01:17:33 -05:00
  • 4a6746a0b1 With single port RAM J 2019-03-03 23:16:35 -05:00
  • a0acbcafdc Add testrom, modified for small memory... enable tests if you need in Makefile J 2019-03-03 20:55:24 -05:00
  • 9e5f83edd9 Add in the test rom J 2019-03-03 19:35:20 -05:00
  • ea1dd551f9 Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used J 2019-03-03 17:29:03 -05:00
  • f35876f9bf Regfile now uses sync ram, -ve clock read. Generics have defaults J 2019-03-03 16:28:34 -05:00
  • eaad427655 Import from the git version found in work/nickg on my trash can mac J 2019-03-03 14:48:57 -05:00