mirror of
https://github.com/kalymos/PsNee.git
synced 2026-03-01 17:47:29 +00:00
refactor: optimize BIOS patching sequence with refined timing nomenclature
Refined the BIOS patching and standardized
timing nomenclature for better technical clarity.
Changes:
- Ad technical documentation within the code.
- Standardized timing variables for better clarity:
- BOOT_OFFSET: Replaces initial checkpoint.
- FOLLOWUP_OFFSET: Replaces initial checkpoint2.
- PULSE_COUNT: Replaces trigger .
- BIT_OFFSET: Replaces hold .
- OVERRIDE: Replaces patching.
This commit is contained in:
kalymos
@@ -3,44 +3,76 @@
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#ifdef BIOS_PATCH
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volatile uint8_t impulse = 0;
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volatile uint8_t patch = 0;
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volatile uint8_t pulse_counter = 0;
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volatile uint8_t patch_done = 0;
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#ifdef INTERRUPT_RISING
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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impulse++;
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if (impulse == TRIGGER){ // If impulse reaches the value defined by TRIGGER, the following actions are performed:
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_delay_us(HOLD);
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PIN_DX_OUTPUT;
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_delay_us(PATCHING);
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/*
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* PHASE 3: Pulse Counting (Inside ISR)
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* The hardware Interrupt Service Routine (ISR) now takes over.
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* It counts the exact number of incoming pulses on PIN_AX until it
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* matches the PULSE_COUNT value.
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*/
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pulse_counter++;
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if (pulse_counter == PULSE_COUNT){ // If pulse_counter reaches the value defined by PULSE_COUNT
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/*
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* PHASE 4: Precision Bit Alignment
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* Once the PULSE_COUNT is reached, a micro-delay (BIT_OFFSET) is applied.
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* This shifts the timing from the clock edge to the exact bit position
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* within the data stream that needs modification.
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*/
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_delay_us(BIT_OFFSET);
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/*
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* PHASE 5: Data Bus Overdrive (The Patch)
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* Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit.
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* This effectively overwrites the BIOS data on-the-fly
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* before reverting the pin to INPUT to release the bus.
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*/
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE);
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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impulse = 0;
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patch = 1; // patch is set to 1, indicating that the first patch is completed.
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pulse_counter = 0;
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patch_done = 1; // patch_done is set to 1, indicating that the first patch is completed.
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}
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}
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void Bios_Patching(){
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/*
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* PHASE 1: Signal Stabilization & Alignment
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* Detects the startup state (Cold Boot vs. Reset).
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* If the line is already HIGH (Cold Boot), we wait for a full LOW-to-HIGH transition
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* to ensure we are aligned with the start of a clean clock cycle.
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*/
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PIN_AX_INTERRUPT_RISING;
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if (PIN_AX_READ != 0) // If the AX pin is high
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if (PIN_AX_READ != 0) // Case: Power-on / Line high (---__-_-_)
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{
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while (PIN_AX_READ != 0); // Wait for it to go low
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while (PIN_AX_READ == 0); // Then wait for it to go high again.
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while (PIN_AX_READ != 0); // Wait for falling edge
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while (PIN_AX_READ == 0); // Wait for next rising edge to sync
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}
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else // If the AX pin is low
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else // Case: Reset / Line low (_____-_-_)
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{
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while (PIN_AX_READ == 0); // Wait for it to go high.
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while (PIN_AX_READ == 0); // Wait for the very first rising edge
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}
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// Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT.
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_delay_ms(CHECKPOINT);
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/*
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* PHASE 2: Reaching the Target Memory Window
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* We introduce a strategic delay (BOOT_OFFSET) to skip initial noise.
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* This points the execution to a known idle gap in the
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* address range calls before the critical data appears.
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* DELAY: |---//-----|
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* AX: -_-_//-_-_________-_-_-_
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*/
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_delay_ms(BOOT_OFFSET);
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// Armed for hardware detection
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PIN_AX_INTERRUPT_RISING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patch != 1); // Wait for the first stage of the patch to complete:
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while (patch_done != 1); // Wait for the first stage of the patch to complete:
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}
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@@ -49,37 +81,37 @@
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#ifdef INTERRUPT_FALLING
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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impulse++;
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if (impulse == TRIGGER){ // If impulse reaches the value defined by TRIGGER, the following actions are performed:
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_delay_us (HOLD);
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pulse_counter++;
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if (pulse_counter == PULSE_COUNT){
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_delay_us (BIT_OFFSET);
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PIN_DX_OUTPUT;
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_delay_us (PATCHING);
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_delay_us (OVERRIDE);
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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impulse = 0;
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patch = 1; // patch is set to 1, indicating that the first patch is completed.
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pulse_counter = 0;
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patch_done = 1;
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}
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}
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void Bios_Patching(){
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PIN_AX_INTERRUPT_FALLING;
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if (PIN_AX_READ != 0) // If the AX pin is high
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if (PIN_AX_READ != 0)
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{
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while (PIN_AX_READ != 0); // Wait for it to go low
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while (PIN_AX_READ == 0); // Then wait for it to go high again.
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while (PIN_AX_READ != 0);
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while (PIN_AX_READ == 0);
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}
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else // If the AX pin is low
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else
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{
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while (PIN_AX_READ == 0); // Wait for it to go high.
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while (PIN_AX_READ == 0);
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}
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_delay_ms(CHECKPOINT); // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT.
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_delay_ms(BOOT_OFFSET); /
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PIN_AX_INTERRUPT_FALLING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patch != 1); // Wait for the first stage of the patch to complete:
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while (patch_done != 1);
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}
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#endif
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@@ -87,67 +119,62 @@
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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impulse++;
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if (impulse == TRIGGER){ // If impulse reaches the value defined by TRIGGER, the following actions are performed:
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_delay_us (HOLD);
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pulse_counter++;
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if (pulse_counter == PULSE_COUNT){
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_delay_us (BIT_OFFSET);
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PIN_DX_SET;
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PIN_DX_OUTPUT;
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_delay_us (PATCHING);
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_delay_us (OVERRIDE);
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PIN_DX_CLEAR;
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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impulse = 0;
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patch = 1; // patch is set to 1, indicating that the first patch is completed.
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pulse_counter = 0;
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patch_done = 1;
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}
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}
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ISR(PIN_AY_INTERRUPT_VECTOR){
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impulse++;
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if (impulse == TRIGGER2) // If impulse reaches the value defined by TRIGGER2, the following actions are performed:
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pulse_counter++;
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if (pulse_counter == PULSE_COUNT_2)
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{
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_delay_us (HOLD2);
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_delay_us (BIT_OFFSET_2);
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PIN_DX_OUTPUT;
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_delay_us (PATCHING2);
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_delay_us (OVERRIDE_2);
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PIN_DX_INPUT;
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PIN_AY_INTERRUPT_DISABLE;
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patch = 2; // patch is set to 2, indicating that the second patch is completed.
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patch_done = 2;
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}
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}
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void Bios_Patching(){
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PIN_AX_INTERRUPT_RISING;
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if (PIN_AX_READ != 0) // If the AX pin is high
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if (PIN_AX_READ != 0)
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{
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while (PIN_AX_READ != 0); // Wait for it to go low
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while (PIN_AX_READ == 0); // Then wait for it to go high again.
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while (PIN_AX_READ != 0);
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while (PIN_AX_READ == 0);
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}
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else // If the AX pin is low
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else
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{
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while (PIN_AX_READ == 0); // Wait for it to go high.
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while (PIN_AX_READ == 0);
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}
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_delay_ms(CHECKPOINT); // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT.
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_delay_ms(BOOT_OFFSET);
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PIN_AX_INTERRUPT_RISING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patch != 1); // Wait for the first stage of the patch to complete:
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while (patch_done != 1);
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while (PIN_AY_READ != 0);
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#ifdef HIGH_PATCH
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PIN_AY_INTERRUPT_FALLING;
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#else
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PIN_AY_INTERRUPT_RISING;
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#endif
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while (PIN_AY_READ != 0); // Wait for it to go low
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_delay_ms(FOLLOWUP_OFFSET);
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_delay_ms(CHECKPOINT2); // Wait until the number of microseconds elapsed reaches a value defined by CHECKPOINT2.
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PIN_AY_INTERRUPT_RISING;
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PIN_AY_INTERRUPT_ENABLE;
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while (patch != 2); // Wait for the second stage of the patch to complete:
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while (patch_done != 2);
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}
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@@ -11,8 +11,8 @@
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1 clock cycle = 1 / 16,000,000 s ≈ 62.5 ns
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1 µs ≈ 16 clock cycles
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HOLD _delay_us(2.75) = 44 clock cycles
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PATCHING _delay_us(0.2) = 3,2 clock cycles
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BIT_OFFSET _delay_us(2.75) = 44 clock cycles
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OVERRIDE _delay_us(0.2) = 3,2 clock cycles
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*/
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@@ -27,93 +27,93 @@
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#ifdef SCPH_102
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#define BIOS_PATCH
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#define INTERRUPT_RISING
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#define CHECKPOINT 83.9
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#define TRIGGER 48
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#define HOLD 2.75
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#define PATCHING 0.2
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#define BOOT_OFFSET 83.9
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#define PULSE_COUNT 48
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#define BIT_OFFSET 2.75
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_100
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#define BIOS_PATCH
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#define INTERRUPT_RISING
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#define CHECKPOINT 83.9 //83.72 - 84.15
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#define TRIGGER 48
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#define HOLD 2.75 //2.63 - 2.87
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#define PATCHING 0.2
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#define BOOT_OFFSET 83.9 //83.72 - 84.15
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#define PULSE_COUNT 48
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#define BIT_OFFSET 2.75 //2.63 - 2.87
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_7500_9000
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#define BIOS_PATCH
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#define INTERRUPT_RISING
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#define CHECKPOINT 75.2 //74.95 - 75.55
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#define TRIGGER 16
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#define HOLD 2.8
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#define PATCHING 0.2
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#define BOOT_OFFSET 75.2 //74.95 - 75.55
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#define PULSE_COUNT 16
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#define BIT_OFFSET 2.8
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_7000
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//#define PATCH_SWITCH
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#define BIOS_PATCH
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#define INTERRUPT_RISING
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#define CHECKPOINT 75.2 //75.3
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#define TRIGGER 16
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#define HOLD 2.8
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#define PATCHING 0.2
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#define BOOT_OFFSET 75.2 //75.3
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#define PULSE_COUNT 16
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#define BIT_OFFSET 2.8
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_5500
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#define BIOS_PATCH
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#define INTERRUPT_FALLING
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#define CHECKPOINT 76.07 //75.99 - 76.14
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#define TRIGGER 21
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#define HOLD 2.8
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#define PATCHING 0.2
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#define BOOT_OFFSET 76.07 //75.99 - 76.14
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#define PULSE_COUNT 21
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#define BIT_OFFSET 2.8
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_5000
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#define BIOS_PATCH
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#define INTERRUPT_FALLING
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#define CHECKPOINT 75.2 //75.12 - 75.27
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#define TRIGGER 21
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#define HOLD 2.8 //2.7 - 2.85
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#define PATCHING 0.1
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#define BOOT_OFFSET 75.2 //75.12 - 75.27
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#define PULSE_COUNT 21
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#define BIT_OFFSET 2.8 //2.7 - 2.85
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#define OVERRIDE 0.1
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#endif
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#ifdef SCPH_3500
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#define BIOS_PATCH
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#define INTERRUPT_FALLING
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#define CHECKPOINT 75.2 //75.12 - 75.27
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#define TRIGGER 21
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#define HOLD 2.75 //2.65 - 2.85
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#define PATCHING 0.2
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#define BOOT_OFFSET 75.2 //75.12 - 75.27
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#define PULSE_COUNT 21
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#define BIT_OFFSET 2.75 //2.65 - 2.85
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_3000
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#define BIOS_PATCH
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#define CHECKPOINT 82.9 //82.65 - 83.26
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#define TRIGGER 60
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#define HOLD 2.7 //2.58 - 2.8
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#define PATCHING 0.15
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#define HIGH_PATCH
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#define INTERRUPT_RISING_HIGH_PATCH
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#define CHECKPOINT2 253.3
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#define TRIGGER2 43
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#define HOLD2 2.88
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#define PATCHING2 0.15
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#define BOOT_OFFSET 82.9 //82.65 - 83.26
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#define PULSE_COUNT 60
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#define BIT_OFFSET 2.7 //2.58 - 2.8
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#define OVERRIDE 0.15
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#define HIGH_PATCH
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#define FOLLOWUP_OFFSET 253.3
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#define PULSE_COUNT_2 43
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#define BIT_OFFSET_2 2.88
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#define OVERRIDE_2 0.15
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#endif
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#ifdef SCPH_1000
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#define BIOS_PATCH
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#define CHECKPOINT 82.9 // 82.63 - 83.26
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#define TRIGGER 92
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#define HOLD 2.65 // 2.58 - 2.75
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#define PATCHING 0.15
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#define HIGH_PATCH
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#define INTERRUPT_RISING_HIGH_PATCH
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#define CHECKPOINT2 272.8
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#define TRIGGER2 71
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#define HOLD2 2.88
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#define PATCHING2 0.15
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#define BOOT_OFFSET 82.9 // 82.63 - 83.26
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#define PULSE_COUNT 92
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#define BIT_OFFSET 2.65 // 2.58 - 2.75
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#define OVERRIDE 0.15
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#define HIGH_PATCH
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#define FOLLOWUP_OFFSET 272.8
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#define PULSE_COUNT_2 71
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#define BIT_OFFSET_2 2.88
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#define OVERRIDE_2 0.15
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#endif
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/*------------------------------------------------------------------------------------------------
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