brad 0e9bfd9d85

2010-04-02 12:36:00 +00:00

cpu

basic focal working

2009-05-10 23:51:20 +00:00

images

basic images for focal

2007-01-03 12:30:31 +00:00

pdf

2010-04-02 12:33:22 +00:00

rtl

2010-04-02 12:30:59 +00:00

sim

boots tss/8

2010-04-02 12:32:05 +00:00

simhv36-1

2010-04-02 12:34:22 +00:00

tss8

2010-04-02 12:36:00 +00:00

utils

2010-04-02 12:32:35 +00:00

v

initial

2007-01-02 16:24:48 +00:00

verif

2010-04-02 12:31:13 +00:00

xilinx

initial

2007-01-02 16:28:10 +00:00

Description

FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source

65 MiB

Languages

Verilog 46.9%

C 39%

Roff 4.1%

C++ 3.4%

Module Management System 1.7%

Other 4.7%