Joerg Hoppe
b2a79c5221
Cleanup
2019-12-19 10:30:45 +01:00
Joerg Hoppe
061dbac5b6
Fast GRANT forwarding, fixes "hang" on 11/84
2019-12-11 08:08:22 +01:00
Joerg Hoppe
130c1f4086
menu ">>>" prompt with menu code
2019-12-08 18:01:36 +01:00
Joerg Hoppe
d70ab0566c
CPU20 diag in comments
2019-12-08 18:00:12 +01:00
Joerg Hoppe
1b90dd73f7
tuning for PCB 2019-12
...
CPU20 diags in comments
2019-12-08 17:58:28 +01:00
Joerg Hoppe
8ec0638b7e
obsolent cmdline param "--arb" removed
2019-12-07 18:34:54 +01:00
Joerg Hoppe
4af9053d94
better signal names
2019-11-23 10:29:16 +01:00
Joerg Hoppe
b0cbeb8ad0
- Fix: got BBSY too early
...
"After receiving the negation of BBSY, SSYN and BGn, the requesting device
asserts BBSY"
- Fixed arbitration for emalated CPU.
2019-11-22 18:22:31 +01:00
Joerg Hoppe
aef4854a88
Fix REQUEST/GRANT/SACK: "A device may not accept a grant (assert SACK) after it passes the grant"
2019-11-02 16:29:17 +01:00
Joerg Hoppe
48f10ed34b
removed RL02 test images from repository
2019-11-01 14:21:39 +01:00
Joerg Hoppe
b3293be2e3
removed big documentation PDFs from repository
2019-11-01 14:11:48 +01:00
Joerg Hoppe
6c9f41dd2b
PRU generated wrong GRANT OUT on REQUEST
2019-11-01 12:33:57 +01:00
Joerg Hoppe
1a1b2d6063
Bugfix manual UNIBUS signal ADDR
2019-10-15 08:24:09 +02:00
Joerg Hoppe
6751f13c91
Removed documenation scans from git repository (faster update)
2019-10-08 19:35:51 +02:00
Joerg Hoppe
10f0540c4a
CPU20 WAIT
2019-10-08 15:05:37 +02:00
Joerg Hoppe
3f71d6f093
CPU20 UNIBUS Interrupt, Experiments to probe UNIBUS arbitrator
2019-10-08 12:36:36 +02:00
Joerg Hoppe
53e22d558c
Missing initialization of sm_arb, causing one-time lock after power-ON
2019-10-05 08:11:29 +02:00
Joerg Hoppe
f314317e2a
DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP
2019-10-04 12:45:26 +02:00
Joerg Hoppe
73b9d2f9fb
Better integration of CPU20 into UniBone framework
2019-09-26 07:54:19 +02:00
Joerg Hoppe
cef911f70b
Better integration of CPU20 into UniBone framework
2019-09-26 07:42:59 +02:00
Joerg Hoppe
43f567024a
Successful INTR on emulated CPU20 with emulated DL11
2019-09-24 14:33:41 +02:00
Joerg Hoppe
b2d944f9cd
First successful iNTR on emulated CPU20
2019-09-23 13:42:47 +02:00
Joerg Hoppe
47bf827c52
typo
2019-09-19 14:06:06 +02:00
Joerg Hoppe
3c011252ab
Reworked inputline()
2019-09-19 13:09:05 +02:00
Joerg Hoppe
07e8e2a96e
removed --debug from .sh-scripts
2019-09-19 13:07:27 +02:00
Joerg Hoppe
9089ee06b6
Reworked inputline()
2019-09-19 13:02:11 +02:00
Joerg Hoppe
bf6d60363c
Reworked inputline()
2019-09-19 13:01:31 +02:00
Joerg Hoppe
b9d28d73c4
Start MSCP test, KW11 without "line monitor bit clear"
2019-09-19 12:58:38 +02:00
Joerg Hoppe
5812d82651
increased max DMA chunk size from 512 to 4K (test, and RAM was free)
2019-09-19 12:56:52 +02:00
Joerg Hoppe
e46b26b497
DL11 / KW11 ZDLD and RSX11 OK
2019-09-19 10:56:43 +02:00
Joerg Hoppe
e102425ebe
32/64 problem, no timeouts > 4.2 secs were possible.
2019-09-05 10:25:32 +02:00
Joerg Hoppe
92714c1ebe
Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11.
...
Also MSCP IOX.
2019-09-02 15:46:54 +02:00
Joerg Hoppe
cc42d60409
type in dir name
2019-09-02 15:37:29 +02:00
Joerg Hoppe
15d22c8e25
/home/joerg/retrocmp/dec/UniBone/workspace
2019-09-01 06:47:30 +02:00
Joerg Hoppe
f13b35bc08
KW11 LKS line monitor bit can only be cleared
2019-08-31 17:29:48 +02:00
Joerg Hoppe
30df58f42c
fix baudrate bit width
2019-08-30 13:38:34 +02:00
Joerg Hoppe
e3ca35f24b
device parameter interurpt vector&level not udpated
2019-08-28 16:45:52 +02:00
Joerg Hoppe
52d646973d
delay after powercycle, so system is stable for next operation
2019-08-28 16:45:08 +02:00
Joerg Hoppe
d058310e53
CPU20 power start/power fail
2019-08-27 19:05:41 +02:00
Joerg Hoppe
6f2adbd216
levelchange(PSW) on RTI
2019-08-27 13:31:37 +02:00
Joerg Hoppe
827515eb8c
module rename for upcoming intr_slave
2019-08-26 13:51:34 +02:00
Joerg Hoppe
ea91180f28
Connected CPU20 to INTR,INIT,Power ON/OFF.
...
PRU INTR routing still do to.
2019-08-25 09:17:28 +02:00
Joerg Hoppe
f938c8ba8a
Power OFF event now from ACLO
...
PRU bugfix: if DMA cycle started by register access cycle
Extended interface for emulated CPU
2019-08-22 17:30:21 +02:00
Joerg Hoppe
fa454f646c
added listing for easy loading
2019-08-19 13:26:22 +02:00
Joerg Hoppe
3d1d9d3cf6
ACLO/DCLO/INIT moved from PRU to ARM
...
INTR/DMA request params linked to device params on change
2019-08-19 13:12:42 +02:00
Joerg Hoppe
e2229871de
PDP-11 test program for concurrent INTR/DMA
...
Serial, Clock, RL02, RK05, MSCP
2019-08-19 12:57:18 +02:00
Joerg Hoppe
8ff33a0be1
Infrastructure for emulated CPUs: Bus arbitrator, Interrupt fielding processor
2019-08-16 19:04:12 +02:00
Jörg Hoppe
155b02a089
Merge pull request #3 from livingcomputermuseum/master
...
Fixes for MSCP with new DMA/IRQ infrastructure
2019-08-16 14:25:44 +02:00
Josh Dersch
6f1b476716
Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait).
...
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
2019-08-16 02:23:32 +02:00
Josh Dersch
073a2334b6
Fixes for MSCP after Joerg's INTR/DMA rewrites:
...
- Fixed programmable interrupt vector (was broken after changes)
- Fixed interrupts during MSCP 4-stage init to atomically update SA register; 4.3bsd now boots.
2019-08-14 09:46:32 +02:00
