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Commit Graph

33 Commits

Author SHA1 Message Date
Joerg Hoppe
ea91180f28 Connected CPU20 to INTR,INIT,Power ON/OFF.
PRU INTR routing still do to.
2019-08-25 09:17:28 +02:00
Joerg Hoppe
f938c8ba8a Power OFF event now from ACLO
PRU bugfix: if DMA cycle started by register access cycle
Extended interface for emulated CPU
2019-08-22 17:30:21 +02:00
Joerg Hoppe
fa454f646c added listing for easy loading 2019-08-19 13:26:22 +02:00
Joerg Hoppe
3d1d9d3cf6 ACLO/DCLO/INIT moved from PRU to ARM
INTR/DMA request params linked to device params on change
2019-08-19 13:12:42 +02:00
Joerg Hoppe
e2229871de PDP-11 test program for concurrent INTR/DMA
Serial, Clock, RL02, RK05, MSCP
2019-08-19 12:57:18 +02:00
Joerg Hoppe
8ff33a0be1 Infrastructure for emulated CPUs: Bus arbitrator, Interrupt fielding processor 2019-08-16 19:04:12 +02:00
Josh Dersch
6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait).
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
2019-08-16 02:23:32 +02:00
Josh Dersch
1d4fe694ae Merge remote-tracking branch 'upstream/master' 2019-08-12 17:28:19 -07:00
Joerg Hoppe
39caffd6e6 Emulated DL11: stream interface parallel to RS232.
demo: "dl11 rcv" and "dl11 wait" script extension
cleanup
2019-08-10 10:19:05 +02:00
Joerg Hoppe
313957631f Cleanup, fixes Interrupt logic, RL11 tests 2019-08-08 07:32:08 +02:00
Joerg Hoppe
855f1a6cee GitHub usability 2019-08-05 09:28:07 +02:00
Joerg Hoppe
d9b49ac70f Fix GitHub repository 2019-08-05 08:37:03 +02:00
Joerg Hoppe
10cf1598f1 Big summer rework:
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
2019-08-02 20:10:48 +02:00
Joerg Hoppe
974aeed8eb Big summer rework:
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
2019-08-02 16:45:54 +02:00
Joerg Hoppe
471df2d8ea PRU1: multiple parallel timeouts 2019-07-03 21:48:49 +02:00
Joerg Hoppe
3f783e5000 Missing source added 2019-07-02 13:02:06 +02:00
Joerg Hoppe
04869fb46f PRU statemachines easier to control from main thread 2019-07-02 07:09:01 +02:00
Joerg Hoppe
81c3295e31 DL11 cleanup&fixes 2019-06-24 17:25:20 +02:00
Joerg Hoppe
4062386b97 Multiple parallel instances of device::worker() possible 2019-06-23 12:00:13 +02:00
Joerg Hoppe
3952cb93b0 Enable devices individually over param "enabled"
UNIBUS addr, intr vector, level setable
2019-06-20 21:58:04 +02:00
Josh Dersch
76166ce7a1 Merge remote-tracking branch 'upstream/master' 2019-06-19 22:26:49 +02:00
Joerg Hoppe
264f6e5085 Cleanup incomplete commits 2019-06-18 21:03:02 +02:00
Josh Dersch
8f72cb2324 Merge remote-tracking branch 'upstream/master'
Conflicts:
	10.03_app_demo/2_src/menu_devices.cpp
2019-06-18 20:54:06 +02:00
Josh Dersch
7626b50c52 Merge remote-tracking branch 'upstream/master'
Conflicts:
	10.01_base/2_src/arm/storagedrive.cpp
	10.01_base/2_src/arm/unibusadapter.cpp
	10.01_base/2_src/arm/unibusadapter.hpp
	10.01_base/2_src/pru1/pru1_statemachine_dma.c
	10.02_devices/2_src/mscp_server.cpp
	10.02_devices/2_src/mscp_server.hpp
	10.02_devices/2_src/rk05.hpp
	10.02_devices/2_src/rk11.cpp
	10.02_devices/2_src/rk11.hpp
	10.02_devices/2_src/rl11.cpp
	10.02_devices/2_src/uda.cpp
	10.03_app_demo/2_src/makefile
	10.03_app_demo/2_src/menu_devices.cpp
2019-06-18 20:50:33 +02:00
Joerg Hoppe
1a79abb89f Cleanup incomplete commits 2019-06-18 20:38:07 +02:00
Joerg Hoppe
db0167afe1 Version 2019-06: many changes
PRU1 code split into multiple images
1. test functions
2. UNIBUS operation

PRU1 bus latch interface
Write byte/bits access not with MACROS (random optimizer influence),
now with *_helper() procedures. Same timing, more determinism, much code saving.
Nono more  ASM code to write PRU0 XFER area.

demo: menu to test UNIBUS signals directly

rework "Arbitration" logic: now 3-fold
Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER
- no Arbitrator (SACK penidng for 11/34 Konsole) (NONE)
- phyiscal PDP_11 CPU is Arbitrator (CLIENT)
- UniBone implements Arbitrator (MASTER)
- Same PRU code loop handles all arbitration types

PRU buslatch timing slower, for some problematic PCBs

 More aggressive bus latch  selftest
 (mixed patterns, running on PRU now)

Refinement of ready-to-run scripts
- Adapted to changed "demo" menu
- new name scheme
<OS>_<boot- drive>_<PDP-11CPU>
indicates
- which OS is run
- which disk emulation is used and what is the boot device
- what is the (minimum) PDP-11 to run that

Merged in Joshs DMA timing for 11/84
UNIBUS master cycles waits 350 us before MSYN, instead 150.

Merged in Joshs DMA request queue
multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially

Merged in Joshs MSCP driver
- Build RT-11v5.5 for MSCP
- added boot loader "du.lst"

MSCP run scrips
2.11BSD on MSCP on PDP-11/44
RT11 on MSCP

Fix: image file sizing
Disk image file exptend automatically if block beyond current file end is written
2019-06-14 16:31:01 +02:00
Josh Dersch
bb546db52a Workaround for low-level DMA issue; give up waiting for DMA transfers if enough time passes.
This works around an as-yet-unexplained PRU bug.
2019-05-09 07:26:55 +02:00
Josh Dersch
c6958e1660 Implemented the last few unimplemented MSCP commands; as yet untested with real PDP-11/VAX code (have yet to find a case that uses them.)
General code cleanup/refactoring.  Added header comments.

Added "use image size" parameter for MSCP disks -- block count derived from image file size rather than DEC drive geometry; allows for arbitrarily large disks (up to 2TB, theoretically.)
2019-05-08 05:34:40 +02:00
Josh Dersch
a00f0592dc Added small workaround for (possible) bug in VMS secondary bootstrap; improved reset behavior.
4.3bsd still panics during uda bringup.
2019-05-07 19:03:49 +02:00
Josh Dersch
be3b6d57ed Implemented AVAILABLE, ERASE, DETERMINE ACCESS PATHS commands. Tweaks to interrupt queueing (request_INTR now blocks until
the interrupt actually gets signaled on the unibus).  OpenVMS 7.3 now boots on the VAX.
2019-05-06 19:28:20 +02:00
Josh Dersch
8eff2a4e10 Rewrote lower-level DMA and IRQ handling: DMA and IRQ requests are now queued and will run to completion on their own
without help from the device code (just call request_DMA and when it returns the DMA transfer is complete.)  Fixed
request_DMA to chunk DMA transfers larger than 1024 bytes to avoid overrunning the mailbox's shared memory.  Fixed
concurrency issues with DMA requests -- a race condition could cause DMA request data to get clobbered.

RT-11 now boots, MSCP behavior is now very reliable.
2019-05-04 03:30:26 +02:00
Josh Dersch
e0aabf2197 Changes to MSCP implementation with tweaks to PRU1 code to allow operation on 11/84 under 2.11BSD.
2.11BSD boots and works well enough to recompile itself.
2019-04-24 20:29:33 +02:00
Joerg Hoppe
2530d9cbb5 Initial 2019-04-05 11:30:26 +02:00