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6f1b476716
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes with latest PRU code -- MSCP works reliably on PDP-11/84 again.
1013 lines
32 KiB
C++
1013 lines
32 KiB
C++
/*
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uda.cpp: Implementation of the MSCP port (unibus interface).
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Copyright Vulcan Inc. 2019 via Living Computers: Museum + Labs, Seattle, WA.
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Contributed under the BSD 2-clause license.
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This provides logic for the UDA50's SA and IP registers,
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the four-step initialization handshake, DMA transfers to and
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from the Unibus, and the command/response ring protocols.
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While the name "UDA" is used here, this is not a strict emulation
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of a real UDA50 -- it is a general MSCP implementation and can be
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thought of as the equivalent of the third-party MSCP controllers
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from Emulex, CMD, etc. that were available.
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At this time this class acts as the port for an MSCP controller.
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It would be trivial to extend this to TMSCP at a future date.
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*/
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#include <string.h>
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#include <assert.h>
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#include "unibus.h"
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#include "unibusadapter.hpp"
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#include "unibusdevice.hpp"
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#include "storagecontroller.hpp"
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#include "mscp_drive.hpp"
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#include "uda.hpp"
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uda_c::uda_c() :
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storagecontroller_c(),
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_server(nullptr),
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_ringBase(0),
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_commandRingLength(0),
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_responseRingLength(0),
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_commandRingPointer(0),
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_responseRingPointer(0),
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_interruptVector(0),
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_interruptEnable(false),
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_purgeInterruptEnable(false),
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_step1Value(0),
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_initStep(InitializationStep::Uninitialized),
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_next_step(false)
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{
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name.value = "uda";
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type_name.value = "UDA50";
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log_label = "uda";
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// base addr, intr-vector, intr level
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set_default_bus_params(0772150, 20, 0154, 5) ;
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dma_request.set_priority_slot(default_priority_slot) ;
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intr_request.set_priority_slot(default_priority_slot) ;
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intr_request.set_level(default_intr_level) ;
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intr_request.set_vector(default_intr_vector) ;
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// The UDA50 controller has two registers.
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register_count = 2;
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IP_reg = &(this->registers[0]); // @ base addr
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strcpy(IP_reg->name, "IP");
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IP_reg->active_on_dati = true;
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IP_reg->active_on_dato = true;
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IP_reg->reset_value = 0;
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IP_reg->writable_bits = 0xffff;
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SA_reg = &(this->registers[1]); // @ base addr + 2
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strcpy(SA_reg->name, "SA");
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SA_reg->active_on_dati = false;
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SA_reg->active_on_dato = true;
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SA_reg->reset_value = 0;
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SA_reg->writable_bits = 0xffff;
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_server.reset(new mscp_server(this));
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//
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// Initialize drives. We support up to eight attached drives.
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//
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drivecount = DRIVE_COUNT;
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for (uint32_t i=0; i<drivecount; i++)
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{
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mscp_drive_c *drive = new mscp_drive_c(this, i);
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drive->unitno.value = i;
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drive->name.value = name.value + std::to_string(i);
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drive->log_label = drive->name.value;
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drive->parent = this;
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storagedrives.push_back(drive);
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}
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}
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uda_c::~uda_c()
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{
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for(uint32_t i=0; i<drivecount; i++)
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{
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delete storagedrives[i];
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}
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storagedrives.clear();
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}
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bool uda_c::on_param_changed(parameter_c *param) {
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// no own parameter or "enable" logic
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return storagecontroller_c::on_param_changed(param) ; // more actions (for enable)
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}
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//
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// Reset():
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// Resets the UDA controller state.
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// Resets the attached MSCP server, which may take
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// significant time.
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//
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void uda_c::Reset(void)
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{
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DEBUG("UDA reset");
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_server->Reset();
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_ringBase = 0;
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_commandRingLength = 0;
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_responseRingLength = 0;
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_commandRingPointer = 0;
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_responseRingPointer = 0;
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_interruptVector = 0;
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intr_vector.value = 0;
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_interruptEnable = false;
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_purgeInterruptEnable = false;
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}
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//
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// GetDriveCount():
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// Returns the number of drives that can be attached to this controller.
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//
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uint32_t uda_c::GetDriveCount(void)
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{
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return drivecount;
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}
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//
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// GetDrive():
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// Returns a pointer to an mscp_drive_c object for the specified drive number.
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// This pointer is owned by the UDA class.
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//
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mscp_drive_c* uda_c::GetDrive(
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uint32_t driveNumber)
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{
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assert(driveNumber < drivecount);
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return dynamic_cast<mscp_drive_c*>(storagedrives[driveNumber]);
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}
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//
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// StateTransition():
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// Transitions the UDA initialization state machine to the specified step,
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// atomically.
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//
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void uda_c::StateTransition(
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InitializationStep nextStep)
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{
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pthread_mutex_lock(&on_after_register_access_mutex);
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_initStep = nextStep;
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_next_step = true;
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pthread_cond_signal(&on_after_register_access_cond);
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pthread_mutex_unlock(&on_after_register_access_mutex);
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}
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//
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// worker():
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// Implements the initialization state machine.
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//
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void uda_c::worker(unsigned instance)
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{
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UNUSED(instance) ; // only one
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worker_init_realtime_priority(rt_device);
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timeout_c timeout;
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while (!workers_terminate)
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{
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//
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// Wait to be awoken.
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//
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pthread_mutex_lock(&on_after_register_access_mutex);
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while (!_next_step)
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{
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pthread_cond_wait(
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&on_after_register_access_cond,
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&on_after_register_access_mutex);
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}
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_next_step = false;
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pthread_mutex_unlock(&on_after_register_access_mutex);
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switch (_initStep)
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{
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case InitializationStep::Uninitialized:
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DEBUG("Transition to Init state Uninitialized.");
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// SA should already be zero but we'll be extra sure here.
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update_SA(0x0);
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// Reset the controller: This may take some time as we must
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// wait for the MSCP server to wrap up its current workitem.
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Reset();
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StateTransition(InitializationStep::Step1);
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break;
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case InitializationStep::Step1:
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timeout.wait_us(500);
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DEBUG("Transition to Init state S1.");
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//
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// S1 is set, all other bits zero. This indicates that we
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// support a host-settable interrupt vector, that we do not
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// implement enhanced diagnostics, and that no errors have
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// occurred.
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//
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update_SA(0x0800);
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break;
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case InitializationStep::Step2:
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timeout.wait_us(500);
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DEBUG("Transition to Init state S2.");
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// Update the SA read value for step 2:
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// S2 is set, unibus port type (0), SA bits 15-8 written
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// by the host in step 1.
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Interrupt(0x1000 | ((_step1Value >> 8) & 0xff));
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break;
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case InitializationStep::Step3:
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timeout.wait_us(500);
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DEBUG("Transition to Init state S3.");
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// Update the SA read value for step 3:
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// S3 set, plus SA bits 7-0 written by the host in step 1.
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Interrupt(0x2000 | (_step1Value & 0xff));
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break;
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case InitializationStep::Step4:
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timeout.wait_us(100);
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// Clear communications area, set SA
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DEBUG("Clearing comm area at 0x%x. Purge header: %d", _ringBase, _purgeInterruptEnable);
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DEBUG("resp 0x%x comm 0x%x", _responseRingLength, _commandRingLength);
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{
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int headerSize = _purgeInterruptEnable ? 8 : 4;
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for(uint32_t i = 0;
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i < (_responseRingLength + _commandRingLength) * sizeof(Descriptor) + headerSize;
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i += 2)
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{
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DMAWriteWord(_ringBase + i - headerSize, 0x0);
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}
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}
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//
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// Set the ownership bit on all descriptors in the response ring
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// to indicate that the port owns them.
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//
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Descriptor blankDescriptor;
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blankDescriptor.Word0.Word0 = 0;
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blankDescriptor.Word1.Word1 = 0;
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blankDescriptor.Word1.Fields.Ownership = 1;
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for(uint32_t i = 0; i < _responseRingLength; i++)
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{
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DMAWrite(
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GetResponseDescriptorAddress(i),
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sizeof(Descriptor),
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reinterpret_cast<uint8_t*>(&blankDescriptor));
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}
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DEBUG("Transition to Init state S4, comm area initialized.");
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// Update the SA read value for step 4:
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// Bits 7-0 indicating our control microcode version.
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Interrupt(UDA50_ID); // UDA50 ID, makes RSTS happy
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break;
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case InitializationStep::Complete:
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DEBUG("Initialization complete.");
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break;
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}
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}
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}
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//
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// on_after_register_access():
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// Handles register accesses for the IP and SA registers.
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//
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void
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uda_c::on_after_register_access(
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unibusdevice_register_t *device_reg,
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uint8_t unibus_control
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)
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{
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switch (device_reg->index)
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{
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case 0: // IP - read / write
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if (UNIBUS_CONTROL_DATO == unibus_control)
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{
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// "When written with any value, it causes a hard initialization
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// of the port and the device controller."
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DEBUG("Reset due to IP read");
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update_SA(0x0);
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StateTransition(InitializationStep::Uninitialized);
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}
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else
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{
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// "When read while the port is operating, it causes the controller
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// to initiate polling..."
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if (_initStep == InitializationStep::Complete)
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{
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DEBUG("Request to start polling.");
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_server->InitPolling();
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}
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}
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break;
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case 1: // SA - write only
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uint16_t value = SA_reg->active_dato_flipflops;
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switch (_initStep)
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{
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case InitializationStep::Uninitialized:
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// Should not occur, we treat it like step1 here.
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DEBUG("Write to SA in Uninitialized state.");
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case InitializationStep::Step1:
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// Host writes the following:
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// 15 13 11 10 8 7 6 0
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// +-+-+-----+-----+-+-------------+
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// |1|W|c rng|r rng|I| int vector |
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// | |R| lng | lng |E|(address / 4)|
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// +-+-+-----+-----+-+-------------+
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// WR = 1 tells the port to enter diagnostic wrap
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// mode (which we ignore).
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//
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// c rng lng is the number of slots (32 bits each)
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// in the command ring, expressed as a power of two.
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//
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// r rng lng is as above, but for the response ring.
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//
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// IE=1 means the host is requesting an interrupt
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// at the end of the completion of init steps 1-3.
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//
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// int vector determines if interrupts will be generated
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// by the port. If this field is non-zero, interupts will
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// be generated during normal operation and, if IE=1,
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// during initialization.
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_step1Value = value;
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_interruptVector = ((value & 0x7f) << 2);
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intr_request.set_vector(_interruptVector);
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_interruptEnable = !!(value & 0x80);
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_responseRingLength = (1 << ((value & 0x700) >> 8));
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_commandRingLength = (1 << ((value & 0x3800) >> 11));
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DEBUG("Step1: 0x%x", value);
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DEBUG("resp ring 0x%x", _responseRingLength);
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DEBUG("cmd ring 0x%x", _commandRingLength);
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DEBUG("vector 0x%x", _interruptVector);
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DEBUG("ie %d", _interruptEnable);
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// Move to step 2.
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StateTransition(InitializationStep::Step2);
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break;
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case InitializationStep::Step2:
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// Host writes the following:
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// 15 1 0
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// +-----------------------------+-+
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// | ringbase low |P|
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// | (address) |I|
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// +-----------------------------+-+
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// ringbase low is the low-order portion of word
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// [ringbase+0] of the communications area. This is a
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// 16-bit byte address whose low-order bit is zero implicitly.
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//
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_ringBase = value & 0xfffe;
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_purgeInterruptEnable = !!(value & 0x1);
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DEBUG("Step2: rb 0x%x pi %d", _ringBase, _purgeInterruptEnable);
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// Move to step 3 and interrupt as necessary.
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StateTransition(InitializationStep::Step3);
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break;
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case InitializationStep::Step3:
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// Host writes the following:
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// 15 0
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// +-+-----------------------------+
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// |P| ringbase hi |
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// |P| (address) |
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// +-+-----------------------------+
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// PP = 1 means the host is requesting execution of
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// purge and poll tests, which we ignore because we can.
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//
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// ringbase hi is the high-order portion of the address
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// [ringbase+0].
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_ringBase |= ((value & 0x7fff) << 16);
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DEBUG("Step3: ringbase 0x%x", _ringBase);
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// Move to step 4 and interrupt as necessary.
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StateTransition(InitializationStep::Step4);
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break;
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case InitializationStep::Step4:
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// Host writes the following:
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// 15 8 7 1 0
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// +---------------+-----------+-+-+
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// | reserved | burst |L|G|
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// | | |F|O|
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// +---------------+-----------+-+-+
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// Burst is one less than the max. number of longwords
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// the host is willing to allow per DMA transfer.
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// If zero, the port uses its default burst count.
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//
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// LF=1 means that the host wants a "last fail" response
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// packet when initialization is complete.
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//
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// GO=1 means that the controller should enter its functional
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// microcode as soon as initialization completes.
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//
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// Note that if GO=0 when initialization completes, the port
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// will continue to read SA until the host forces SA bit 0 to
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// make the transition 0->1.
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//
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// There is no explicit interrupt at the end of Step 4.
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//
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// TODO: For now we ignore burst settings.
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// We also ignore Last Fail report requests since we aren't
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// supporting onboard diagnostics and there's nothing to
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// report.
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//
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DEBUG("Step4: 0x%x", value);
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if (value & 0x1)
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{
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//
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// GO is set, move to the Complete state. The worker will
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// start the controller running.
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//
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StateTransition(InitializationStep::Complete);
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// The VMS bootstrap expects SA to be zero IMMEDIATELY
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// after completion.
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update_SA(0x0);
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}
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else
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{
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// GO unset, wait until it is.
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}
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break;
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case InitializationStep::Complete:
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// "When zeroed by the host during both initialization and normal
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// operation, it signals the port that the host has successfully
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// completed a bus adapter purge in response to a port-initiated
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// purge request.
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// We don't deal with bus adapter purges, yet.
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break;
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}
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break;
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}
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}
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//
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// update_SA():
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// Updates the SA register value exposed by the Unibone.
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//
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void
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uda_c::update_SA(uint16_t value)
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{
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set_register_dati_value(
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SA_reg,
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value,
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"update_SA");
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}
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//
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// GetNextCommand():
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// Attempts to pull the next command from the command ring, if any
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// are available.
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// If successful, returns a pointer to a Message struct; this pointer
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// is owned by the caller.
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// On failure, nullptr is returned. This indicates that the ring is
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// empty or that an attempt to access non-existent memory occurred.
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// TODO: Need to handle NXM cases properly.
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//
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Message*
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uda_c::GetNextCommand(void)
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{
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timeout_c timer;
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// Grab the next descriptor being pointed to
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uint32_t descriptorAddress =
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GetCommandDescriptorAddress(_commandRingPointer);
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DEBUG("Next descriptor (ring ptr 0x%x) address is o%o",
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_commandRingPointer,
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descriptorAddress);
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std::unique_ptr<Descriptor> cmdDescriptor(
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reinterpret_cast<Descriptor*>(
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DMARead(
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descriptorAddress,
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sizeof(Descriptor),
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sizeof(Descriptor))));
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// TODO: if NULL is returned after retry assume a bus error and handle it appropriately.
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assert(cmdDescriptor != nullptr);
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// Check owner bit: if set, ownership has been passed to us, in which case
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// we can attempt to pull the actual message from memory.
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if (cmdDescriptor->Word1.Fields.Ownership)
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{
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bool doInterrupt = false;
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uint32_t messageAddress =
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cmdDescriptor->Word0.EnvelopeLow |
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(cmdDescriptor->Word1.Fields.EnvelopeHigh << 16);
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DEBUG("Next message address is o%o, flag %d",
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messageAddress, cmdDescriptor->Word1.Fields.Flag);
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//
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// Grab the message length; this is at messageAddress - 4
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//
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bool success = false;
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uint16_t messageLength =
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DMAReadWord(
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messageAddress - 4,
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success);
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assert(messageLength > 0 && messageLength < MAX_MESSAGE_LENGTH);
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std::unique_ptr<Message> cmdMessage(
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reinterpret_cast<Message*>(
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DMARead(
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messageAddress - 4,
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messageLength + 4,
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sizeof(Message))));
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|
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//
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// Handle Ring Transitions (from full to not-full) and associated
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// interrupts.
|
|
// If the previous entry in the ring is owned by the Port then that indicates
|
|
// that the ring was previously full (i.e. the descriptor we're now returning
|
|
// is the first free entry.)
|
|
//
|
|
if (cmdDescriptor->Word1.Fields.Flag)
|
|
{
|
|
//
|
|
// Flag is set, host is requesting a transition interrupt.
|
|
// Check the previous entry in the ring.
|
|
//
|
|
if (_commandRingLength == 1)
|
|
{
|
|
// Degenerate case: If the ring is of size 1 we always interrupt.
|
|
doInterrupt = true;
|
|
}
|
|
else
|
|
{
|
|
uint32_t previousDescriptorAddress =
|
|
GetCommandDescriptorAddress(
|
|
(_commandRingPointer - 1) % _commandRingLength);
|
|
|
|
std::unique_ptr<Descriptor> previousDescriptor(
|
|
reinterpret_cast<Descriptor*>(
|
|
DMARead(
|
|
previousDescriptorAddress,
|
|
sizeof(Descriptor),
|
|
sizeof(Descriptor))));
|
|
|
|
if (previousDescriptor->Word1.Fields.Ownership)
|
|
{
|
|
// We own the previous descriptor, so the ring was previously
|
|
// full.
|
|
doInterrupt = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Message retrieved; reset the Owner bit of the command descriptor,
|
|
// set the Flag bit (to indicate that we've processed it)
|
|
// and return a pointer to the message.
|
|
//
|
|
cmdDescriptor->Word1.Fields.Ownership = 0;
|
|
cmdDescriptor->Word1.Fields.Flag = 1;
|
|
DMAWrite(
|
|
descriptorAddress,
|
|
sizeof(Descriptor),
|
|
reinterpret_cast<uint8_t*>(cmdDescriptor.get()));
|
|
|
|
//
|
|
// Move to the next descriptor in the ring for next time.
|
|
_commandRingPointer = (_commandRingPointer + 1) % _commandRingLength;
|
|
|
|
// Post an interrupt as necessary.
|
|
if (doInterrupt)
|
|
{
|
|
//
|
|
// Set ring base - 4 to non-zero to indicate a transition.
|
|
//
|
|
DMAWriteWord(_ringBase - 4, 0x1);
|
|
Interrupt();
|
|
}
|
|
|
|
return cmdMessage.release();
|
|
}
|
|
|
|
DEBUG("No descriptor found. 0x%x 0x%x", cmdDescriptor->Word0.Word0, cmdDescriptor->Word1.Word1);
|
|
|
|
// No descriptor available.
|
|
return nullptr;
|
|
}
|
|
|
|
//
|
|
// PostResponse():
|
|
// Posts the provided Message to the response ring.
|
|
// Returns true on success, false otherwise.
|
|
// TODO: Need to handle NXM, as above.
|
|
//
|
|
bool
|
|
uda_c::PostResponse(
|
|
Message* response
|
|
)
|
|
{
|
|
bool res = false;
|
|
|
|
// Grab the next descriptor.
|
|
uint32_t descriptorAddress = GetResponseDescriptorAddress(_responseRingPointer);
|
|
std::unique_ptr<Descriptor> cmdDescriptor(
|
|
reinterpret_cast<Descriptor*>(
|
|
DMARead(
|
|
descriptorAddress,
|
|
sizeof(Descriptor),
|
|
sizeof(Descriptor))));
|
|
|
|
// TODO: if NULL is returned assume a bus error and handle it appropriately.
|
|
|
|
//
|
|
// Check owner bit: if set, ownership has been passed to us, in which case
|
|
// we can use this descriptor and fill in the response buffer it points to.
|
|
// If not, we return false to indicate to the caller the need to try again later.
|
|
//
|
|
if (cmdDescriptor->Word1.Fields.Ownership)
|
|
{
|
|
bool doInterrupt = false;
|
|
|
|
uint32_t messageAddress =
|
|
cmdDescriptor->Word0.EnvelopeLow |
|
|
(cmdDescriptor->Word1.Fields.EnvelopeHigh << 16);
|
|
|
|
//
|
|
// Read the buffer length the host has allocated for this response.
|
|
//
|
|
// TODO:
|
|
// If it is shorter than the buffer we're writing then we will need to
|
|
// split the response into multiple responses. I have never seen this happen,
|
|
// however and I'm curious if the documentation (AA-L621A-TK) is simply incorrect:
|
|
// "Note that if a controller's responses are less than or equal to 60 bytes,
|
|
// then the controller need not check the size of the response slot."
|
|
// All of the MSCP response messages are shorter than 60 bytes, so this is always
|
|
// the case. I'll also note that the spec states "The minimum acceptable size
|
|
// is 60 bytes of message text" for the response buffer set up by the host and this
|
|
// is *definitely* not followed by host drivers.
|
|
//
|
|
// The doc is also not exactly clear what a fragmented set of responses looks like...
|
|
//
|
|
// Message length is at messageAddress - 4 -- this is the size of the command
|
|
// not including the two header words.
|
|
//
|
|
bool success = false;
|
|
uint16_t messageLength =
|
|
DMAReadWord(
|
|
messageAddress - 4,
|
|
success);
|
|
|
|
DEBUG("response address o%o length o%o", messageAddress, response->MessageLength);
|
|
|
|
assert(reinterpret_cast<uint16_t*>(response)[0] > 0);
|
|
|
|
if (messageLength == 0)
|
|
{
|
|
// A lot of bootstraps appear to set up response buffers of length 0.
|
|
// We just log the behavior.
|
|
DEBUG("Host response buffer size is zero.");
|
|
}
|
|
else if (messageLength < response->MessageLength)
|
|
{
|
|
//
|
|
// If this happens it's likely fatal since we're not fragmenting responses (see the big comment
|
|
// block above). So eat flaming death.
|
|
// Note: the VMS bootstrap does this, so we'll just log the issue.
|
|
//
|
|
DEBUG("Response buffer 0x%x > host buffer length 0x%x", response->MessageLength, messageLength);
|
|
}
|
|
|
|
//
|
|
// This will fit; simply copy the response message over the top
|
|
// of the buffer allocated on the host -- this updates the header fields
|
|
// as necessary and provides the actual response data to the host.
|
|
//
|
|
DMAWrite(
|
|
messageAddress - 4,
|
|
response->MessageLength + 4,
|
|
reinterpret_cast<uint8_t*>(response));
|
|
|
|
//
|
|
// Check if a transition from empty to non-empty occurred, interrupt if requested.
|
|
//
|
|
// If the previous entry in the ring is owned by the Port then that indicates
|
|
// that the ring was previously empty (i.e. the descriptor we're now returning
|
|
// is the first entry returned to the ring by the Port.)
|
|
//
|
|
if (cmdDescriptor->Word1.Fields.Flag)
|
|
{
|
|
//
|
|
// Flag is set, host is requesting a transition interrupt.
|
|
// Check the previous entry in the ring.
|
|
//
|
|
if (_responseRingLength == 1)
|
|
{
|
|
// Degenerate case: If the ring is of size 1 we always interrupt.
|
|
doInterrupt = true;
|
|
}
|
|
else
|
|
{
|
|
uint32_t previousDescriptorAddress =
|
|
GetResponseDescriptorAddress(
|
|
(_responseRingPointer - 1) % _responseRingLength);
|
|
|
|
std::unique_ptr<Descriptor> previousDescriptor(
|
|
reinterpret_cast<Descriptor*>(
|
|
DMARead(
|
|
previousDescriptorAddress,
|
|
sizeof(Descriptor),
|
|
sizeof(Descriptor))));
|
|
|
|
if (previousDescriptor->Word1.Fields.Ownership)
|
|
{
|
|
// We own the previous descriptor, so the ring was previously
|
|
// full.
|
|
doInterrupt = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Message posted; reset the Owner bit of the response descriptor,
|
|
// and set the Flag bit (to indicate that we've processed it).
|
|
//
|
|
cmdDescriptor->Word1.Fields.Ownership = 0;
|
|
cmdDescriptor->Word1.Fields.Flag = 1;
|
|
DMAWrite(
|
|
descriptorAddress,
|
|
sizeof(Descriptor),
|
|
reinterpret_cast<uint8_t*>(cmdDescriptor.get()));
|
|
|
|
// Post an interrupt as necessary.
|
|
if (doInterrupt)
|
|
{
|
|
DEBUG("Response ring no longer empty, interrupting.");
|
|
//
|
|
// Set ring base - 2 to non-zero to indicate a transition.
|
|
//
|
|
DMAWriteWord(_ringBase - 2, 0x1);
|
|
Interrupt();
|
|
}
|
|
|
|
res = true;
|
|
|
|
// Move to the next descriptor in the ring for next time.
|
|
_responseRingPointer = (_responseRingPointer + 1) % _responseRingLength;
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
//
|
|
// GetControllerIdentifier():
|
|
// Returns the ID used by SET CONTROLLER CHARACTERISTICS.
|
|
// This should be unique per controller.
|
|
//
|
|
uint32_t
|
|
uda_c::GetControllerIdentifier()
|
|
{
|
|
// TODO: make this not hardcoded
|
|
// ID 0x12345678
|
|
return 0x12345678;
|
|
}
|
|
|
|
//
|
|
// GetControllerClassModel():
|
|
// Returns the Class and Model information used by SET CONTROLLER CHARACTERISTICS.
|
|
//
|
|
uint16_t
|
|
uda_c::GetControllerClassModel()
|
|
{
|
|
return 0x0102; // Class 1 (mass storage), model 2 (UDA50)
|
|
}
|
|
|
|
//
|
|
// Interrupt():
|
|
// Invokes a Unibus interrupt if interrupts are enabled and the interrupt
|
|
// vector is non-zero. Updates SA to the specified value atomically.
|
|
//
|
|
void
|
|
uda_c::Interrupt(uint16_t sa_value)
|
|
{
|
|
if ((_interruptEnable || _initStep == InitializationStep::Complete) && _interruptVector != 0)
|
|
{
|
|
unibusadapter->INTR(intr_request, SA_reg, sa_value);
|
|
}
|
|
else
|
|
{
|
|
update_SA(sa_value);
|
|
}
|
|
}
|
|
|
|
//
|
|
// Interrupt():
|
|
// Invokes a Unibus interrupt if interrupts are enabled and the interrupt
|
|
// vector is non-zero.
|
|
//
|
|
void
|
|
uda_c::Interrupt(void)
|
|
{
|
|
if ((_interruptEnable || _initStep == InitializationStep::Complete) && _interruptVector != 0)
|
|
{
|
|
unibusadapter->INTR(intr_request, NULL, 0);
|
|
}
|
|
}
|
|
|
|
//
|
|
// on_power_changed():
|
|
// Resets the controller and all attached drives.
|
|
//
|
|
void
|
|
uda_c::on_power_changed(void)
|
|
{
|
|
storagecontroller_c::on_power_changed();
|
|
|
|
if (power_down)
|
|
{
|
|
DEBUG("Reset due to power change");
|
|
StateTransition(InitializationStep::Uninitialized);
|
|
}
|
|
}
|
|
|
|
//
|
|
// on_init_changed():
|
|
// Resets the controller and all attached drives.
|
|
//
|
|
void
|
|
uda_c::on_init_changed(void)
|
|
{
|
|
if (init_asserted)
|
|
{
|
|
DEBUG("Reset due to INIT");
|
|
StateTransition(InitializationStep::Uninitialized);
|
|
}
|
|
|
|
storagecontroller_c::on_init_changed();
|
|
}
|
|
|
|
//
|
|
// on_drive_status_changed():
|
|
// A no-op. The controller doesn't require any drive notifications.
|
|
//
|
|
void
|
|
uda_c::on_drive_status_changed(storagedrive_c *drive)
|
|
{
|
|
UNUSED(drive);
|
|
}
|
|
|
|
//
|
|
// GetCommandDescriptorAddress():
|
|
// Returns the address of the given command descriptor in the command ring.
|
|
//
|
|
uint32_t
|
|
uda_c::GetCommandDescriptorAddress(
|
|
size_t index
|
|
)
|
|
{
|
|
return _ringBase + _responseRingLength * sizeof(Descriptor) +
|
|
index * sizeof(Descriptor);
|
|
}
|
|
|
|
//
|
|
// GetResponseDescriptorAddress():
|
|
// Returns the address of the given response descriptor in the response ring.
|
|
//
|
|
uint32_t
|
|
uda_c::GetResponseDescriptorAddress(
|
|
size_t index
|
|
)
|
|
{
|
|
return _ringBase + index * sizeof(Descriptor);
|
|
}
|
|
|
|
//
|
|
// DMAWriteWord():
|
|
// Writes a single word to Unibus memory. Returns true
|
|
// on success; if false is returned this is due to an NXM condition.
|
|
//
|
|
bool
|
|
uda_c::DMAWriteWord(
|
|
uint32_t address,
|
|
uint16_t word)
|
|
{
|
|
return DMAWrite(
|
|
address,
|
|
sizeof(uint16_t),
|
|
reinterpret_cast<uint8_t*>(&word));
|
|
}
|
|
|
|
//
|
|
// DMAReadWord():
|
|
// Read a single word from Unibus memory. Returns the word read on success.
|
|
// the success field indicates the success or failure of the read.
|
|
//
|
|
uint16_t
|
|
uda_c::DMAReadWord(
|
|
uint32_t address,
|
|
bool& success)
|
|
{
|
|
uint8_t* buffer = DMARead(
|
|
address,
|
|
sizeof(uint16_t),
|
|
sizeof(uint16_t));
|
|
|
|
if (buffer)
|
|
{
|
|
success = true;
|
|
uint16_t retval = *reinterpret_cast<uint16_t *>(buffer);
|
|
delete[] buffer;
|
|
return retval;
|
|
}
|
|
else
|
|
{
|
|
success = false;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
//
|
|
// DMAWrite():
|
|
// Write data from the provided buffer to Unibus memory. Returns true
|
|
// on success; if false is returned this is due to an NXM condition.
|
|
// The address specified in 'address' must be word-aligned and the
|
|
// length must be even.
|
|
//
|
|
bool
|
|
uda_c::DMAWrite(
|
|
uint32_t address,
|
|
size_t lengthInBytes,
|
|
uint8_t* buffer)
|
|
{
|
|
assert ((lengthInBytes % 2) == 0);
|
|
assert (address < 0x40000);
|
|
|
|
unibusadapter->DMA(dma_request, true,
|
|
UNIBUS_CONTROL_DATO,
|
|
address,
|
|
reinterpret_cast<uint16_t*>(buffer),
|
|
lengthInBytes >> 1);
|
|
return dma_request.success ;
|
|
}
|
|
|
|
//
|
|
// DMARead():
|
|
// Read data from Unibus memory into the returned buffer.
|
|
// Buffer returned is nullptr if memory could not be read.
|
|
// Caller is responsible for freeing the buffer when done.
|
|
// The address specified in 'address' must be word-aligned
|
|
// and the length must be even.
|
|
//
|
|
uint8_t*
|
|
uda_c::DMARead(
|
|
uint32_t address,
|
|
size_t lengthInBytes,
|
|
size_t bufferSize)
|
|
{
|
|
assert (bufferSize >= lengthInBytes);
|
|
assert((lengthInBytes % 2) == 0);
|
|
assert (address < 0x40000);
|
|
|
|
uint16_t* buffer = new uint16_t[bufferSize >> 1];
|
|
|
|
assert(buffer);
|
|
|
|
memset(reinterpret_cast<uint8_t*>(buffer), 0xc3, bufferSize);
|
|
|
|
unibusadapter->DMA(dma_request, true,
|
|
UNIBUS_CONTROL_DATI,
|
|
address,
|
|
buffer,
|
|
lengthInBytes >> 1);
|
|
|
|
if (dma_request.success)
|
|
{
|
|
return reinterpret_cast<uint8_t*>(buffer);
|
|
}
|
|
else
|
|
{
|
|
return nullptr;
|
|
}
|
|
}
|