12 Commits

Author	SHA1	Message	Date
Andrew Kay	cc7023d35f	Cleanup	2020-02-11 07:51:10 -06:00
Andrew Kay	13eb0f52bd	Adding tx_inverted and updating pins	2020-02-10 22:26:39 -06:00
Andrew Kay	ff200bf26f	Adding tx_delay	2020-02-10 22:13:55 -06:00
Andrew Kay	7bf43eede5	Remove BIT_ALIGN state and improve active	2020-02-10 21:56:35 -06:00
Andrew Kay	05663ab5b7	End sequence	2020-02-09 14:53:23 -06:00
Andrew Kay	7a78447c6c	Cleanup clocks	2020-02-09 09:50:40 -06:00
Andrew Kay	42a46806c8	Parity bit	2020-02-09 09:35:00 -06:00
Andrew Kay	77821b3f11	Data	2020-02-08 20:03:13 -06:00
Andrew Kay	b9ed29bd4b	Code violation and sync bit	2020-02-08 19:03:36 -06:00
Andrew Kay	9faae78fd8	Quiesce pattern	2020-02-08 18:55:11 -06:00
Andrew Kay	0b618d6b35	Adding a 19 MHz clock	2020-02-08 17:43:09 -06:00
Andrew Kay	ad7ba12d2c	Verilog templating	2020-02-04 22:11:14 -06:00