Andrew Kay d8464625e7 Cleanup internal_data name

2020-07-05 17:00:19 -05:00

..

.gitignore

Verilog templating

2020-02-04 22:11:14 -06:00

coax_rx_bit_timer.v

testing rx_coax_bit_timer on TinyFPGA

2020-06-21 18:52:21 -05:00

coax_rx.v

Cleanup internal_data name

2020-07-05 17:00:19 -05:00

Makefile

First hardware test of coax_rx, increase clk frequency

2020-07-05 16:13:36 -05:00

pins.pcf

Add data bus

2020-07-05 16:43:39 -05:00

top.v

Add data bus

2020-07-05 16:43:39 -05:00