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sim: sim_halfword: handle HRR/HRRI/HRRM/HRRS, add unit tests
This commit is contained in:
Mikael Pettersson
parent
187178e48a
commit
4d4ab138e6
@ -349,6 +349,10 @@ dispatch(Core, Mem, IR, EA) ->
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8#535 -> sim_halfword:handle_HRLEI(Core, Mem, IR, EA);
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8#536 -> sim_halfword:handle_HRLEM(Core, Mem, IR, EA);
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8#537 -> sim_halfword:handle_HRLES(Core, Mem, IR, EA);
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8#540 -> sim_halfword:handle_HRR(Core, Mem, IR, EA);
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8#541 -> sim_halfword:handle_HRRI(Core, Mem, IR, EA);
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8#542 -> sim_halfword:handle_HRRM(Core, Mem, IR, EA);
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8#543 -> sim_halfword:handle_HRRS(Core, Mem, IR, EA);
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_ ->
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PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
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{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
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@ -53,6 +53,10 @@
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, handle_HRLZ/4
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, handle_HRLZM/4
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, handle_HRLZS/4
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, handle_HRR/4
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, handle_HRRI/4
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, handle_HRRM/4
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, handle_HRRS/4
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]).
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-include("sim_core.hrl").
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@ -408,6 +412,55 @@ handle_HRLES(Core, Mem, IR, EA) ->
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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%% HRR - Half Word Right to Right
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-spec handle_HRR(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRR(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_right(CA, get_right(CE)),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HRRI(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRRI(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_right(CA, EA#ea.offset),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
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-spec handle_HRRM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRRM(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_right(CE, get_right(CA)),
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handle_writeback(Core, Mem, EA, Word);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HRRS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRRS(Core, Mem, IR, EA) ->
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%% The manual states: "If A is zero, HRRS is a no-op (that writes in memory);
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%% otherwise, it is equivalent to MOVE." This is a contradictory statement:
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%% a MOVE A,E reads E but does not write to it. Compare with HLLI, which has
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%% a similar statement without the "(that writes in memory)" part. For
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%% consistency, treat HRRS like HLLS. Alternatively both should perform the
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%% redundant reads and writes, but then they are not equivalent to MOVE.
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handle_HLLS(Core, Mem, IR, EA).
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%% Miscellaneous ===============================================================
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handle_writeback(Core, Mem, EA, Word) ->
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@ -445,3 +498,5 @@ set_left_extend(Left) ->
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set_left_ones(Left) -> (Left bsl 18) bor ((1 bsl 18) - 1).
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set_left_zeros(Left) -> Left bsl 18.
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set_right(Word, Right) -> (Word band (((1 bsl 18) - 1) bsl 18)) bor Right.
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@ -77,6 +77,10 @@
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-define(OP_HRLEI, 8#535).
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-define(OP_HRLEM, 8#536).
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-define(OP_HRLES, 8#537).
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-define(OP_HRR, 8#540).
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-define(OP_HRRI, 8#541).
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-define(OP_HRRM, 8#542).
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-define(OP_HRRS, 8#543).
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%% 2.8 Half-Word Data Transmission =============================================
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@ -567,6 +571,62 @@ hrles_no_ac_test() ->
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, {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1
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]).
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%% HRR - Half Word Right to Right
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hrr_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HRR, 1, 0, 0, 8#200)} % 1,,101/ HRR 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 1)} % AC1 = 1,,1
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]).
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hrri_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 0,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HRRI, 1, 0, 0, 1)} % 0,,101/ HRRI 1,1
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, {1, 8#102, ?INSN_INVALID} % 0,,102/ <invalid>
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 1)} % AC1 = 1,,1
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]).
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hrrm_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HRRM, 1, 0, 0, 8#200)} % 1,,101/ HRRM 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(1, 1)} % C(1,200) = 1,,1
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]).
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hrrs_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HRRS, 1, 0, 0, 8#200)} % 1,,101/ HRRS 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
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]).
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hrrs_no_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1
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, {1, 8#101, ?INSN(?OP_HRRS, 0, 0, 0, 8#200)} % 1,,101/ HRRS 0,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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