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sim: sim_halfword: handle HRRZ/HRRZM/HRRZS, sim_core: handle HRRZI as MOVEI, add unit tests
This commit is contained in:
Mikael Pettersson
parent
4d4ab138e6
commit
ba24bbbbf1
@ -353,6 +353,10 @@ dispatch(Core, Mem, IR, EA) ->
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8#541 -> sim_halfword:handle_HRRI(Core, Mem, IR, EA);
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8#542 -> sim_halfword:handle_HRRM(Core, Mem, IR, EA);
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8#543 -> sim_halfword:handle_HRRS(Core, Mem, IR, EA);
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8#550 -> sim_halfword:handle_HRRZ(Core, Mem, IR, EA);
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8#551 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % HRRZI = MOVEI
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8#552 -> sim_halfword:handle_HRRZM(Core, Mem, IR, EA);
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8#553 -> sim_halfword:handle_HRRZS(Core, Mem, IR, EA);
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_ ->
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PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
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{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
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@ -57,6 +57,9 @@
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, handle_HRRI/4
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, handle_HRRM/4
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, handle_HRRS/4
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, handle_HRRZ/4
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, handle_HRRZM/4
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, handle_HRRZS/4
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]).
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-include("sim_core.hrl").
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@ -461,6 +464,42 @@ handle_HRRS(Core, Mem, IR, EA) ->
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%% redundant reads and writes, but then they are not equivalent to MOVE.
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handle_HLLS(Core, Mem, IR, EA).
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%% HRRZ - Half Word Right to Right, Zeros
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-spec handle_HRRZ(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRRZ(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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Word = get_right(CE),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HRRZM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRRZM(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = get_right(CA),
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handle_writeback(Core, Mem, EA, Word).
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-spec handle_HRRZS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HRRZS(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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Word = get_right(CE),
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handle_writeback(Core, Mem, AC, EA, Word);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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%% Miscellaneous ===============================================================
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handle_writeback(Core, Mem, EA, Word) ->
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@ -81,6 +81,10 @@
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-define(OP_HRRI, 8#541).
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-define(OP_HRRM, 8#542).
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-define(OP_HRRS, 8#543).
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-define(OP_HRRZ, 8#550).
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-define(OP_HRRZI, 8#551).
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-define(OP_HRRZM, 8#552).
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-define(OP_HRRZS, 8#553).
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%% 2.8 Half-Word Data Transmission =============================================
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@ -627,6 +631,64 @@ hrrs_no_ac_test() ->
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[ {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0
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]).
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%% HRRZ - Half Word Right to Right, Zeros
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hrrz_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HRRZ, 1, 0, 0, 8#200)} % 1,,101/ HRRZ 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
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]).
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hrrzi_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 0,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HRRZI, 1, 0, 0, 1)} % 0,,101/ HRRZI 1,1
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, {1, 8#102, ?INSN_INVALID} % 0,,102/ <invalid>
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
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]).
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hrrzm_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HRRZM, 1, 0, 0, 8#200)} % 1,,101/ HRRZM 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,200) = 0,,1
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]).
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hrrzs_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HRRZS, 1, 0, 0, 8#200)} % 1,,101/ HRRZS 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 1)} % 1,,200/ 1,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1
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, {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
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]).
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hrrzs_no_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1
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, {1, 8#101, ?INSN(?OP_HRRZS, 0, 0, 0, 8#200)} % 1,,101/ HRRZS 0,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 1)} % 1,,200/ 1,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1
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, {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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