sim: sim_halfword: handle HRRZ/HRRZM/HRRZS, sim_core: handle HRRZI as MOVEI, add unit tests

This commit is contained in:
Mikael Pettersson
2020-07-27 19:43:37 +02:00
parent 4d4ab138e6
commit ba24bbbbf1
3 changed files with 105 additions and 0 deletions

View File

@@ -353,6 +353,10 @@ dispatch(Core, Mem, IR, EA) ->
8#541 -> sim_halfword:handle_HRRI(Core, Mem, IR, EA);
8#542 -> sim_halfword:handle_HRRM(Core, Mem, IR, EA);
8#543 -> sim_halfword:handle_HRRS(Core, Mem, IR, EA);
8#550 -> sim_halfword:handle_HRRZ(Core, Mem, IR, EA);
8#551 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % HRRZI = MOVEI
8#552 -> sim_halfword:handle_HRRZM(Core, Mem, IR, EA);
8#553 -> sim_halfword:handle_HRRZS(Core, Mem, IR, EA);
_ ->
PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}

View File

@@ -57,6 +57,9 @@
, handle_HRRI/4
, handle_HRRM/4
, handle_HRRS/4
, handle_HRRZ/4
, handle_HRRZM/4
, handle_HRRZS/4
]).
-include("sim_core.hrl").
@@ -461,6 +464,42 @@ handle_HRRS(Core, Mem, IR, EA) ->
%% redundant reads and writes, but then they are not equivalent to MOVE.
handle_HLLS(Core, Mem, IR, EA).
%% HRRZ - Half Word Right to Right, Zeros
-spec handle_HRRZ(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRRZ(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
Word = get_right(CE),
sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
-spec handle_HRRZM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRRZM(Core, Mem, IR, EA) ->
AC = IR band 8#17,
CA = sim_core:get_ac(Core, AC),
Word = get_right(CA),
handle_writeback(Core, Mem, EA, Word).
-spec handle_HRRZS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRRZS(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
Word = get_right(CE),
handle_writeback(Core, Mem, AC, EA, Word);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
%% Miscellaneous ===============================================================
handle_writeback(Core, Mem, EA, Word) ->